Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 4e447ff1 authored by Philipp Zabel's avatar Philipp Zabel Committed by Mauro Carvalho Chehab
Browse files

[media] coda: move cache setup into coda9_set_frame_cache, also use it in start_encoding 



The frame cache should be set up correctly to encode NV12 source frames.
This was not done before, so move the cache setup out of start_decoding
into its own function and call it from both start_encoding and
start_decoding.

Signed-off-by: default avatarPhilipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: default avatarHans Verkuil <hans.verkuil@cisco.com>
Signed-off-by: default avatarMauro Carvalho Chehab <mchehab@osg.samsung.com>
parent cde29ef3

drivers/media/platform/coda/coda-bit.c

+25 −20
Original line number Diff line number Diff line
@@ -721,6 +721,26 @@ int coda_check_firmware(struct coda_dev *dev) 
	return ret;

}



static void coda9_set_frame_cache(struct coda_ctx *ctx, u32 fourcc)

{

	u32 cache_size, cache_config;



	/* Luma 2x0 page, 2x6 cache, chroma 2x0 page, 2x4 cache size */

	cache_size = 0x20262024;

	cache_config = 2 << CODA9_CACHE_PAGEMERGE_OFFSET;

	coda_write(ctx->dev, cache_size, CODA9_CMD_SET_FRAME_CACHE_SIZE);

	if (fourcc == V4L2_PIX_FMT_NV12) {

		cache_config |= 32 << CODA9_CACHE_LUMA_BUFFER_SIZE_OFFSET |

				16 << CODA9_CACHE_CR_BUFFER_SIZE_OFFSET |

				0 << CODA9_CACHE_CB_BUFFER_SIZE_OFFSET;

	} else {

		cache_config |= 32 << CODA9_CACHE_LUMA_BUFFER_SIZE_OFFSET |

				8 << CODA9_CACHE_CR_BUFFER_SIZE_OFFSET |

				8 << CODA9_CACHE_CB_BUFFER_SIZE_OFFSET;

	}

	coda_write(ctx->dev, cache_config, CODA9_CMD_SET_FRAME_CACHE_CONFIG);

}



/*

 * Encoder context operations

 */
@@ -1049,6 +1069,8 @@ static int coda_start_encoding(struct coda_ctx *ctx) 
			coda_write(dev, ctx->iram_info.buf_btp_use,

					CODA9_CMD_SET_FRAME_AXI_BTP_ADDR);



			coda9_set_frame_cache(ctx, q_data_src->fourcc);



			/* FIXME */

			coda_write(dev, ctx->internal_frames[2].paddr,

				   CODA9_CMD_SET_FRAME_SUBSAMP_A);
@@ -1606,30 +1628,13 @@ static int __coda_start_decoding(struct coda_ctx *ctx) 
				CODA7_CMD_SET_FRAME_AXI_DBKC_ADDR);

		coda_write(dev, ctx->iram_info.buf_ovl_use,

				CODA7_CMD_SET_FRAME_AXI_OVL_ADDR);

		if (dev->devtype->product == CODA_960)

		if (dev->devtype->product == CODA_960) {

			coda_write(dev, ctx->iram_info.buf_btp_use,

					CODA9_CMD_SET_FRAME_AXI_BTP_ADDR);

	}



	if (dev->devtype->product == CODA_960) {

		int cbb_size, crb_size;



			coda_write(dev, -1, CODA9_CMD_SET_FRAME_DELAY);

		/* Luma 2x0 page, 2x6 cache, chroma 2x0 page, 2x4 cache size */

		coda_write(dev, 0x20262024, CODA9_CMD_SET_FRAME_CACHE_SIZE);



		if (dst_fourcc == V4L2_PIX_FMT_NV12) {

			cbb_size = 0;

			crb_size = 16;

		} else {

			cbb_size = 8;

			crb_size = 8;

		}

		coda_write(dev, 2 << CODA9_CACHE_PAGEMERGE_OFFSET |

				32 << CODA9_CACHE_LUMA_BUFFER_SIZE_OFFSET |

				cbb_size << CODA9_CACHE_CB_BUFFER_SIZE_OFFSET |

				crb_size << CODA9_CACHE_CR_BUFFER_SIZE_OFFSET,

				CODA9_CMD_SET_FRAME_CACHE_CONFIG);

			coda9_set_frame_cache(ctx, dst_fourcc);

		}

	}



	if (src_fourcc == V4L2_PIX_FMT_H264) {