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Commit 4e3b95f1 authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'qed-Advance-to-FW-8.33.1.0' 



Tomer Tayar says:

====================
qed*: Advance to FW 8.33.1.0

This series advances all qed* drivers to use firmware 8.33.1.0 which brings
new capabilities and initial support of new HW. The changes are mostly in
qed, and include changes in the FW interface files, as well as updating the
FW initialization and debug collection code. The protocol drivers have
minor functional changes for this firmware.

Patch 1 Rearranges and refactors the FW interface files in preparation of
the new FW (no functional change).
Patch 2 Prepares the code for support of new HW (no functional change).
Patch 3 Actual utilization of the new FW.
Patch 4 Advances drivers' version.

v3->v4:
Fix a compilation issue which was reported by krobot (dependency on CRC8).

v2->v3:
Resend the series with a fixed title in the cover letter.

v1->v2:
- Break the previous single patch into several patches.
- Fix compilation issues which were reported by krobot.
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents bbb6189d 41e87c91

drivers/infiniband/hw/qedr/main.c

+1 −1
Original line number Diff line number Diff line
@@ -264,7 +264,7 @@ static int qedr_register_device(struct qedr_dev *dev) 
static int qedr_alloc_mem_sb(struct qedr_dev *dev,

			     struct qed_sb_info *sb_info, u16 sb_id)

{

	struct status_block *sb_virt;

	struct status_block_e4 *sb_virt;

	dma_addr_t sb_phys;

	int rc;

drivers/infiniband/hw/qedr/qedr_hsi_rdma.h

+71 −54
Original line number Diff line number Diff line
@@ -164,6 +164,13 @@ struct rdma_srq_sge { 
	__le32 l_key;

};



/* Rdma doorbell data for flags update */

struct rdma_pwm_flags_data {

	__le16 icid; /* internal CID */

	u8 agg_flags; /* aggregative flags */

	u8 reserved;

};



/* Rdma doorbell data for SQ and RQ */

struct rdma_pwm_val16_data {

	__le16 icid;
@@ -184,8 +191,12 @@ struct rdma_pwm_val32_data { 
#define RDMA_PWM_VAL32_DATA_AGG_CMD_SHIFT		0

#define RDMA_PWM_VAL32_DATA_BYPASS_EN_MASK		0x1

#define RDMA_PWM_VAL32_DATA_BYPASS_EN_SHIFT		2

#define RDMA_PWM_VAL32_DATA_RESERVED_MASK   0x1F

#define RDMA_PWM_VAL32_DATA_RESERVED_SHIFT  3

#define RDMA_PWM_VAL32_DATA_CONN_TYPE_IS_IWARP_MASK	0x1

#define RDMA_PWM_VAL32_DATA_CONN_TYPE_IS_IWARP_SHIFT	3

#define RDMA_PWM_VAL32_DATA_SET_16B_VAL_MASK		0x1

#define RDMA_PWM_VAL32_DATA_SET_16B_VAL_SHIFT		4

#define RDMA_PWM_VAL32_DATA_RESERVED_MASK		0x7

#define RDMA_PWM_VAL32_DATA_RESERVED_SHIFT		5

	__le32 value;

};
@@ -492,9 +503,11 @@ struct rdma_sq_fmr_wqe { 
#define RDMA_SQ_FMR_WQE_DIF_VALIDATE_APP_TAG_SHIFT	5

#define RDMA_SQ_FMR_WQE_DIF_CRC_SEED_MASK		0x1

#define RDMA_SQ_FMR_WQE_DIF_CRC_SEED_SHIFT		6

#define RDMA_SQ_FMR_WQE_RESERVED4_MASK               0x1FF

#define RDMA_SQ_FMR_WQE_RESERVED4_SHIFT              7

	__le32 Reserved5;

#define RDMA_SQ_FMR_WQE_DIF_RX_REF_TAG_CONST_MASK	0x1

#define RDMA_SQ_FMR_WQE_DIF_RX_REF_TAG_CONST_SHIFT	7

#define RDMA_SQ_FMR_WQE_RESERVED4_MASK			0xFF

#define RDMA_SQ_FMR_WQE_RESERVED4_SHIFT			8

	__le32 reserved5;

};



/* First element (16 bytes) of fmr wqe */
@@ -572,9 +585,11 @@ struct rdma_sq_fmr_wqe_3rd { 
#define RDMA_SQ_FMR_WQE_3RD_DIF_VALIDATE_APP_TAG_SHIFT		5

#define RDMA_SQ_FMR_WQE_3RD_DIF_CRC_SEED_MASK			0x1

#define RDMA_SQ_FMR_WQE_3RD_DIF_CRC_SEED_SHIFT			6

#define RDMA_SQ_FMR_WQE_3RD_RESERVED4_MASK               0x1FF

#define RDMA_SQ_FMR_WQE_3RD_RESERVED4_SHIFT              7

	__le32 Reserved5;

#define RDMA_SQ_FMR_WQE_3RD_DIF_RX_REF_TAG_CONST_MASK		0x1

#define RDMA_SQ_FMR_WQE_3RD_DIF_RX_REF_TAG_CONST_SHIFT		7

#define RDMA_SQ_FMR_WQE_3RD_RESERVED4_MASK			0xFF

#define RDMA_SQ_FMR_WQE_RESERVED4_SHIFT				8

	__le32 reserved5;

};



struct rdma_sq_local_inv_wqe {
@@ -618,8 +633,10 @@ struct rdma_sq_rdma_wqe { 
#define RDMA_SQ_RDMA_WQE_INLINE_FLG_SHIFT	4

#define RDMA_SQ_RDMA_WQE_DIF_ON_HOST_FLG_MASK	0x1

#define RDMA_SQ_RDMA_WQE_DIF_ON_HOST_FLG_SHIFT	5

#define RDMA_SQ_RDMA_WQE_RESERVED0_MASK                 0x3

#define RDMA_SQ_RDMA_WQE_RESERVED0_SHIFT                6

#define RDMA_SQ_RDMA_WQE_READ_INV_FLG_MASK	0x1

#define RDMA_SQ_RDMA_WQE_READ_INV_FLG_SHIFT	6

#define RDMA_SQ_RDMA_WQE_RESERVED0_MASK		0x1

#define RDMA_SQ_RDMA_WQE_RESERVED0_SHIFT	7

	u8 wqe_size;

	u8 prev_wqe_size;

	struct regpair remote_va;

drivers/net/ethernet/qlogic/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -85,6 +85,7 @@ config QED 
	tristate "QLogic QED 25/40/100Gb core driver"

	depends on PCI

	select ZLIB_INFLATE

	select CRC8

	---help---

	  This enables the support for ...

drivers/net/ethernet/qlogic/qed/qed.h

+6 −6
Original line number Diff line number Diff line
@@ -53,9 +53,9 @@ 
extern const struct qed_common_ops qed_common_ops_pass;



#define QED_MAJOR_VERSION		8

#define QED_MINOR_VERSION               10

#define QED_REVISION_VERSION            11

#define QED_ENGINEERING_VERSION 21

#define QED_MINOR_VERSION		33

#define QED_REVISION_VERSION		0

#define QED_ENGINEERING_VERSION		20



#define QED_VERSION						 \

	((QED_MAJOR_VERSION << 24) | (QED_MINOR_VERSION << 16) | \
@@ -778,8 +778,8 @@ static inline u8 qed_concrete_to_sw_fid(struct qed_dev *cdev, 
	return sw_fid;

}



#define PURE_LB_TC 8

#define PKT_LB_TC	9

#define MAX_NUM_VOQS_E4	20



int qed_configure_vport_wfq(struct qed_dev *cdev, u16 vp_id, u32 rate);

void qed_configure_vp_wfq_on_link_change(struct qed_dev *cdev,

drivers/net/ethernet/qlogic/qed/qed_cxt.c

+21 −16
Original line number Diff line number Diff line
@@ -86,22 +86,22 @@ 


/* connection context union */

union conn_context {

	struct core_conn_context core_ctx;

	struct eth_conn_context eth_ctx;

	struct iscsi_conn_context iscsi_ctx;

	struct fcoe_conn_context fcoe_ctx;

	struct roce_conn_context roce_ctx;

	struct e4_core_conn_context core_ctx;

	struct e4_eth_conn_context eth_ctx;

	struct e4_iscsi_conn_context iscsi_ctx;

	struct e4_fcoe_conn_context fcoe_ctx;

	struct e4_roce_conn_context roce_ctx;

};



/* TYPE-0 task context - iSCSI, FCOE */

union type0_task_context {

	struct iscsi_task_context iscsi_ctx;

	struct fcoe_task_context fcoe_ctx;

	struct e4_iscsi_task_context iscsi_ctx;

	struct e4_fcoe_task_context fcoe_ctx;

};



/* TYPE-1 task context - ROCE */

union type1_task_context {

	struct rdma_task_context roce_ctx;

	struct e4_rdma_task_context roce_ctx;

};



struct src_ent {
@@ -110,7 +110,7 @@ struct src_ent { 
};



#define CDUT_SEG_ALIGNMET		3 /* in 4k chunks */

#define CDUT_SEG_ALIGNMET_IN_BYTES (1 << (CDUT_SEG_ALIGNMET + 12))

#define CDUT_SEG_ALIGNMET_IN_BYTES	BIT(CDUT_SEG_ALIGNMET + 12)



#define CONN_CXT_SIZE(p_hwfn) \

	ALIGNED_TYPE_SIZE(union conn_context, p_hwfn)
@@ -742,7 +742,7 @@ int qed_cxt_cfg_ilt_compute(struct qed_hwfn *p_hwfn, u32 *line_count) 
	p_blk = qed_cxt_set_blk(&p_cli->pf_blks[0]);



	qed_cxt_qm_iids(p_hwfn, &qm_iids);

	total = qed_qm_pf_mem_size(p_hwfn->rel_pf_id, qm_iids.cids,

	total = qed_qm_pf_mem_size(qm_iids.cids,

				   qm_iids.vf_cids, qm_iids.tids,

				   p_hwfn->qm_info.num_pqs,

				   p_hwfn->qm_info.num_vf_pqs);
@@ -1496,20 +1496,24 @@ static void qed_cdu_init_pf(struct qed_hwfn *p_hwfn) 
	}

}



void qed_qm_init_pf(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)

void qed_qm_init_pf(struct qed_hwfn *p_hwfn,

		    struct qed_ptt *p_ptt, bool is_pf_loading)

{

	struct qed_qm_pf_rt_init_params params;

	struct qed_qm_info *qm_info = &p_hwfn->qm_info;

	struct qed_qm_pf_rt_init_params params;

	struct qed_mcp_link_state *p_link;

	struct qed_qm_iids iids;



	memset(&iids, 0, sizeof(iids));

	qed_cxt_qm_iids(p_hwfn, &iids);



	p_link = &QED_LEADING_HWFN(p_hwfn->cdev)->mcp_info->link_output;



	memset(&params, 0, sizeof(params));

	params.port_id = p_hwfn->port_id;

	params.pf_id = p_hwfn->rel_pf_id;

	params.max_phys_tcs_per_port = qm_info->max_phys_tcs_per_port;

	params.is_first_pf = p_hwfn->first_on_engine;

	params.is_pf_loading = is_pf_loading;

	params.num_pf_cids = iids.cids;

	params.num_vf_cids = iids.vf_cids;

	params.num_tids = iids.tids;
@@ -1520,6 +1524,7 @@ void qed_qm_init_pf(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 
	params.num_vports = qm_info->num_vports;

	params.pf_wfq = qm_info->pf_wfq;

	params.pf_rl = qm_info->pf_rl;

	params.link_speed = p_link->speed;

	params.pq_params = qm_info->qm_pq_params;

	params.vport_params = qm_info->qm_vport_params;
@@ -1883,7 +1888,7 @@ void qed_cxt_hw_init_common(struct qed_hwfn *p_hwfn) 


void qed_cxt_hw_init_pf(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)

{

	qed_qm_init_pf(p_hwfn, p_ptt);

	qed_qm_init_pf(p_hwfn, p_ptt, true);

	qed_cm_init_pf(p_hwfn);

	qed_dq_init_pf(p_hwfn);

	qed_cdu_init_pf(p_hwfn);
@@ -2326,7 +2331,7 @@ qed_cxt_dynamic_ilt_alloc(struct qed_hwfn *p_hwfn, 
		for (elem_i = 0; elem_i < elems_per_p; elem_i++) {

			elem = (union type1_task_context *)elem_start;

			SET_FIELD(elem->roce_ctx.tdif_context.flags1,

				  TDIF_TASK_CONTEXT_REFTAGMASK, 0xf);

				  TDIF_TASK_CONTEXT_REF_TAG_MASK, 0xf);

			elem_start += TYPE1_TASK_CXT_SIZE(p_hwfn);

		}

	}