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Commit 4e03f628 authored by Masahiro Yamada's avatar Masahiro Yamada Committed by Ulf Hansson
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mmc: sdhci-cadence: fix bit shift of read data from PHY port 



This macro is currently unused, but it may be useful for debug use.
Fix it just in case.

Fixes: ff6af28f ("mmc: sdhci-cadence: add Cadence SD4HC support")
Signed-off-by: default avatarMasahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: default avatarAdrian Hunter <adrian.hunter@intel.com>
Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
parent 006cac82

drivers/mmc/host/sdhci-cadence.c

+1 −1
Original line number Diff line number Diff line
@@ -26,7 +26,7 @@ 
#define   SDHCI_CDNS_HRS04_ACK			BIT(26)

#define   SDHCI_CDNS_HRS04_RD			BIT(25)

#define   SDHCI_CDNS_HRS04_WR			BIT(24)

#define   SDHCI_CDNS_HRS04_RDATA_SHIFT		12

#define   SDHCI_CDNS_HRS04_RDATA_SHIFT		16

#define   SDHCI_CDNS_HRS04_WDATA_SHIFT		8

#define   SDHCI_CDNS_HRS04_ADDR_SHIFT		0