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Commit 4dd964df authored by Kishon Vijay Abraham I's avatar Kishon Vijay Abraham I Committed by Bjorn Helgaas
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PCI: designware: Look for configuration space in 'reg', not 'ranges' 



The configuration address space has so far been specified in *ranges*,
however it should be specified in *reg* making it a platform MEM resource.
Hence used 'platform_get_resource_*' API to get configuration address space
in the designware driver.

Signed-off-by: default avatarKishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
Acked-by: default avatarMohit Kumar <mohit.kumar@st.com>
Acked-by: default avatarJingoo Han <jg1.han@samsung.com>
Cc: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Arnd Bergmann <arnd@arndb.de>
parent 7171511e

Documentation/devicetree/bindings/pci/designware-pcie.txt

+4 −0
Original line number Diff line number Diff line
@@ -2,6 +2,10 @@ 


Required properties:

- compatible: should contain "snps,dw-pcie" to identify the core.

- reg: Should contain the configuration address space.

- reg-names: Must be "config" for the PCIe configuration space.

    (The old way of getting the configuration address space from "ranges"

    is deprecated and should be avoided.)

- #address-cells: set to <3>

- #size-cells: set to <2>

- device_type: set to "pci"

drivers/pci/host/pcie-designware.c

+15 −2
Original line number Diff line number Diff line
@@ -20,6 +20,7 @@ 
#include <linux/of_pci.h>

#include <linux/pci.h>

#include <linux/pci_regs.h>

#include <linux/platform_device.h>

#include <linux/types.h>



#include "pcie-designware.h"
@@ -396,11 +397,23 @@ static const struct irq_domain_ops msi_domain_ops = { 
int __init dw_pcie_host_init(struct pcie_port *pp)

{

	struct device_node *np = pp->dev->of_node;

	struct platform_device *pdev = to_platform_device(pp->dev);

	struct of_pci_range range;

	struct of_pci_range_parser parser;

	struct resource *cfg_res;

	u32 val;

	int i;



	cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config");

	if (cfg_res) {

		pp->config.cfg0_size = resource_size(cfg_res)/2;

		pp->config.cfg1_size = resource_size(cfg_res)/2;

		pp->cfg0_base = cfg_res->start;

		pp->cfg1_base = cfg_res->start + pp->config.cfg0_size;

	} else {

		dev_err(pp->dev, "missing *config* reg space\n");

	}



	if (of_pci_range_parser_init(&parser, np)) {

		dev_err(pp->dev, "missing ranges property\n");

		return -EINVAL;
@@ -433,6 +446,8 @@ int __init dw_pcie_host_init(struct pcie_port *pp) 
			of_pci_range_to_resource(&range, np, &pp->cfg);

			pp->config.cfg0_size = resource_size(&pp->cfg)/2;

			pp->config.cfg1_size = resource_size(&pp->cfg)/2;

			pp->cfg0_base = pp->cfg.start;

			pp->cfg1_base = pp->cfg.start + pp->config.cfg0_size;

		}

	}
@@ -445,8 +460,6 @@ int __init dw_pcie_host_init(struct pcie_port *pp) 
		}

	}



	pp->cfg0_base = pp->cfg.start;

	pp->cfg1_base = pp->cfg.start + pp->config.cfg0_size;

	pp->mem_base = pp->mem.start;



	pp->va_cfg0_base = devm_ioremap(pp->dev, pp->cfg0_base,