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Commit 4dd8ee5d authored by Paul Burton's avatar Paul Burton Committed by Ralf Baechle
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MIPS: Add CP0 CMGCRBase definitions & accessor 



The CMGCRBase register is defined by the PRA specification as an optional
register which indicates the physical base of the MIPS Coherence Manager
Global Control Register block. This patch simply adds a definition for
the base address field within the register, along with an accessor
function for reading the register.

Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6356/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 20a8d5d5

arch/mips/include/asm/mipsregs.h

+6 −0
Original line number Diff line number Diff line
@@ -671,6 +671,10 @@ 
/*  EntryHI bit definition */

#define MIPS_ENTRYHI_EHINV	(_ULCAST_(1) << 10)



/* CMGCRBase bit definitions */

#define MIPS_CMGCRB_BASE	11

#define MIPS_CMGCRF_BASE	(~_ULCAST_((1 << MIPS_CMGCRB_BASE) - 1))



/*

 * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.

 */
@@ -1025,6 +1029,8 @@ do { \ 


#define read_c0_prid()		__read_32bit_c0_register($15, 0)



#define read_c0_cmgcrbase()	__read_ulong_c0_register($15, 3)



#define read_c0_config()	__read_32bit_c0_register($16, 0)

#define read_c0_config1()	__read_32bit_c0_register($16, 1)

#define read_c0_config2()	__read_32bit_c0_register($16, 2)