Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 4db134a3 authored by oulijun's avatar oulijun Committed by Jason Gunthorpe
Browse files

RDMA/hns: Update the implementation of set_gid 



This patch updates the implementation of set_gid by using
command queue instead of directly writing registers.

Signed-off-by: default avatarLijun Ou <oulijun@huawei.com>
Signed-off-by: default avatarYixian Liu <liuyixian@huawei.com>
Signed-off-by: default avatarWei Hu (Xavier) <xavier.huwei@huawei.com>
Signed-off-by: default avatarJason Gunthorpe <jgg@mellanox.com>
parent ded58ff9

drivers/infiniband/hw/hns/hns_roce_common.h

+0 −6
Original line number Original line Diff line number Diff line
@@ -385,12 +385,6 @@ 
#define ROCEE_VF_SMAC_CFG0_REG			0x12000

#define ROCEE_VF_SMAC_CFG0_REG			0x12000

#define ROCEE_VF_SMAC_CFG1_REG			0x12004

#define ROCEE_VF_SMAC_CFG1_REG			0x12004





#define ROCEE_VF_SGID_CFG0_REG			0x10000

#define ROCEE_VF_SGID_CFG1_REG			0x10004

#define ROCEE_VF_SGID_CFG2_REG			0x10008

#define ROCEE_VF_SGID_CFG3_REG			0x1000c

#define ROCEE_VF_SGID_CFG4_REG			0x10010



#define ROCEE_VF_ABN_INT_CFG_REG		0x13000

#define ROCEE_VF_ABN_INT_CFG_REG		0x13000

#define ROCEE_VF_ABN_INT_ST_REG			0x13004

#define ROCEE_VF_ABN_INT_ST_REG			0x13004

#define ROCEE_VF_ABN_INT_EN_REG			0x13008

#define ROCEE_VF_ABN_INT_EN_REG			0x13008

drivers/infiniband/hw/hns/hns_roce_hw_v2.c

+38 −24
Original line number Original line Diff line number Diff line
@@ -1536,13 +1536,45 @@ static int hns_roce_v2_chk_mbox(struct hns_roce_dev *hr_dev, 
	return 0;

	return 0;

}

}





static int hns_roce_config_sgid_table(struct hns_roce_dev *hr_dev,

				      int gid_index, const union ib_gid *gid,

				      enum hns_roce_sgid_type sgid_type)

{

	struct hns_roce_cmq_desc desc;

	struct hns_roce_cfg_sgid_tb *sgid_tb =

				    (struct hns_roce_cfg_sgid_tb *)desc.data;

	u32 *p;



	hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_SGID_TB, false);



	roce_set_field(sgid_tb->table_idx_rsv,

		       CFG_SGID_TB_TABLE_IDX_M,

		       CFG_SGID_TB_TABLE_IDX_S, gid_index);

	roce_set_field(sgid_tb->vf_sgid_type_rsv,

		       CFG_SGID_TB_VF_SGID_TYPE_M,

		       CFG_SGID_TB_VF_SGID_TYPE_S, sgid_type);



	p = (u32 *)&gid->raw[0];

	sgid_tb->vf_sgid_l = cpu_to_le32(*p);



	p = (u32 *)&gid->raw[4];

	sgid_tb->vf_sgid_ml = cpu_to_le32(*p);



	p = (u32 *)&gid->raw[8];

	sgid_tb->vf_sgid_mh = cpu_to_le32(*p);



	p = (u32 *)&gid->raw[0xc];

	sgid_tb->vf_sgid_h = cpu_to_le32(*p);



	return hns_roce_cmq_send(hr_dev, &desc, 1);

}



static int hns_roce_v2_set_gid(struct hns_roce_dev *hr_dev, u8 port,

static int hns_roce_v2_set_gid(struct hns_roce_dev *hr_dev, u8 port,

			       int gid_index, const union ib_gid *gid,

			       int gid_index, const union ib_gid *gid,

			       const struct ib_gid_attr *attr)

			       const struct ib_gid_attr *attr)

{

{

	enum hns_roce_sgid_type sgid_type = GID_TYPE_FLAG_ROCE_V1;

	enum hns_roce_sgid_type sgid_type = GID_TYPE_FLAG_ROCE_V1;

	u32 *p;

	int ret;

	u32 val;





	if (!gid || !attr)

	if (!gid || !attr)

		return -EINVAL;

		return -EINVAL;
@@ -1557,29 +1589,11 @@ static int hns_roce_v2_set_gid(struct hns_roce_dev *hr_dev, u8 port, 
			sgid_type = GID_TYPE_FLAG_ROCE_V2_IPV6;

			sgid_type = GID_TYPE_FLAG_ROCE_V2_IPV6;

	}

	}





	p = (u32 *)&gid->raw[0];

	ret = hns_roce_config_sgid_table(hr_dev, gid_index, gid, sgid_type);

	roce_raw_write(*p, hr_dev->reg_base + ROCEE_VF_SGID_CFG0_REG +

	if (ret)

		       0x20 * gid_index);

		dev_err(hr_dev->dev, "Configure sgid table failed(%d)!\n", ret);



	p = (u32 *)&gid->raw[4];

	roce_raw_write(*p, hr_dev->reg_base + ROCEE_VF_SGID_CFG1_REG +

		       0x20 * gid_index);



	p = (u32 *)&gid->raw[8];

	roce_raw_write(*p, hr_dev->reg_base + ROCEE_VF_SGID_CFG2_REG +

		       0x20 * gid_index);



	p = (u32 *)&gid->raw[0xc];

	roce_raw_write(*p, hr_dev->reg_base + ROCEE_VF_SGID_CFG3_REG +

		       0x20 * gid_index);



	val = roce_read(hr_dev, ROCEE_VF_SGID_CFG4_REG + 0x20 * gid_index);

	roce_set_field(val, ROCEE_VF_SGID_CFG4_SGID_TYPE_M,

		       ROCEE_VF_SGID_CFG4_SGID_TYPE_S, sgid_type);



	roce_write(hr_dev, ROCEE_VF_SGID_CFG4_REG + 0x20 * gid_index, val);





	return 0;

	return ret;

}

}





static int hns_roce_v2_set_mac(struct hns_roce_dev *hr_dev, u8 phy_port,

static int hns_roce_v2_set_mac(struct hns_roce_dev *hr_dev, u8 phy_port,

drivers/infiniband/hw/hns/hns_roce_hw_v2.h

+15 −3
Original line number Original line Diff line number Diff line
@@ -205,6 +205,7 @@ enum hns_roce_opcode_type { 
	HNS_ROCE_OPC_ALLOC_VF_RES			= 0x8401,

	HNS_ROCE_OPC_ALLOC_VF_RES			= 0x8401,

	HNS_ROCE_OPC_CFG_EXT_LLM			= 0x8403,

	HNS_ROCE_OPC_CFG_EXT_LLM			= 0x8403,

	HNS_ROCE_OPC_CFG_TMOUT_LLM			= 0x8404,

	HNS_ROCE_OPC_CFG_TMOUT_LLM			= 0x8404,

	HNS_ROCE_OPC_CFG_SGID_TB			= 0x8500,

	HNS_ROCE_OPC_CFG_BT_ATTR			= 0x8506,

	HNS_ROCE_OPC_CFG_BT_ATTR			= 0x8506,

};

};
@@ -1245,9 +1246,6 @@ struct hns_roce_vf_res_b { 
#define ROCEE_VF_SMAC_CFG1_VF_SMAC_H_S 0

#define ROCEE_VF_SMAC_CFG1_VF_SMAC_H_S 0

#define ROCEE_VF_SMAC_CFG1_VF_SMAC_H_M GENMASK(15, 0)

#define ROCEE_VF_SMAC_CFG1_VF_SMAC_H_M GENMASK(15, 0)





#define ROCEE_VF_SGID_CFG4_SGID_TYPE_S 0

#define ROCEE_VF_SGID_CFG4_SGID_TYPE_M GENMASK(1, 0)



struct hns_roce_cfg_bt_attr {

struct hns_roce_cfg_bt_attr {

	__le32 vf_qpc_cfg;

	__le32 vf_qpc_cfg;

	__le32 vf_srqc_cfg;

	__le32 vf_srqc_cfg;
@@ -1292,6 +1290,20 @@ struct hns_roce_cfg_bt_attr { 
#define CFG_BT_ATTR_DATA_3_VF_MPT_HOPNUM_S 8

#define CFG_BT_ATTR_DATA_3_VF_MPT_HOPNUM_S 8

#define CFG_BT_ATTR_DATA_3_VF_MPT_HOPNUM_M GENMASK(9, 8)

#define CFG_BT_ATTR_DATA_3_VF_MPT_HOPNUM_M GENMASK(9, 8)





struct hns_roce_cfg_sgid_tb {

	__le32	table_idx_rsv;

	__le32	vf_sgid_l;

	__le32	vf_sgid_ml;

	__le32	vf_sgid_mh;

	__le32	vf_sgid_h;

	__le32	vf_sgid_type_rsv;

};

#define CFG_SGID_TB_TABLE_IDX_S 0

#define CFG_SGID_TB_TABLE_IDX_M GENMASK(7, 0)



#define CFG_SGID_TB_VF_SGID_TYPE_S 0

#define CFG_SGID_TB_VF_SGID_TYPE_M GENMASK(1, 0)



struct hns_roce_cmq_desc {

struct hns_roce_cmq_desc {

	__le16 opcode;

	__le16 opcode;

	__le16 flag;

	__le16 flag;