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Commit 4da1c677 authored by Poddar, Sourav's avatar Poddar, Sourav Committed by Tero Kristo
Browse files

ARM: dts: am43x-clock: add tbclk data for ehrpwm 



We need "tbclk" clock data for the functioning of ehrpwm
module. Hence, populating the required clock information
in clock dts file.

Signed-off-by: default avatarSourav Poddar <sourav.poddar@ti.com>
Acked-by: default avatarTero Kristo <t-kristo@ti.com>
Signed-off-by: default avatarTero Kristo <t-kristo@ti.com>
parent 9e100eba

arch/arm/boot/dts/am43xx-clocks.dtsi

+48 −0
Original line number Diff line number Diff line
@@ -87,6 +87,54 @@ 
		clock-mult = <1>;

		clock-div = <1>;

	};



	ehrpwm0_tbclk: ehrpwm0_tbclk {

		#clock-cells = <0>;

		compatible = "ti,gate-clock";

		clocks = <&dpll_per_m2_ck>;

		ti,bit-shift = <0>;

		reg = <0x0664>;

	};



	ehrpwm1_tbclk: ehrpwm1_tbclk {

		#clock-cells = <0>;

		compatible = "ti,gate-clock";

		clocks = <&dpll_per_m2_ck>;

		ti,bit-shift = <1>;

		reg = <0x0664>;

	};



	ehrpwm2_tbclk: ehrpwm2_tbclk {

		#clock-cells = <0>;

		compatible = "ti,gate-clock";

		clocks = <&dpll_per_m2_ck>;

		ti,bit-shift = <2>;

		reg = <0x0664>;

	};



	ehrpwm3_tbclk: ehrpwm3_tbclk {

		#clock-cells = <0>;

		compatible = "ti,gate-clock";

		clocks = <&dpll_per_m2_ck>;

		ti,bit-shift = <4>;

		reg = <0x0664>;

	};



	ehrpwm4_tbclk: ehrpwm4_tbclk {

		#clock-cells = <0>;

		compatible = "ti,gate-clock";

		clocks = <&dpll_per_m2_ck>;

		ti,bit-shift = <5>;

		reg = <0x0664>;

	};



	ehrpwm5_tbclk: ehrpwm5_tbclk {

		#clock-cells = <0>;

		compatible = "ti,gate-clock";

		clocks = <&dpll_per_m2_ck>;

		ti,bit-shift = <6>;

		reg = <0x0664>;

	};

};

&prcm_clocks {

	clk_32768_ck: clk_32768_ck {

drivers/clk/ti/clk-43xx.c

+6 −0
Original line number Diff line number Diff line
@@ -105,6 +105,12 @@ static struct ti_dt_clk am43xx_clks[] = { 
	DT_CLK(NULL, "func_12m_clk", "func_12m_clk"),

	DT_CLK(NULL, "vtp_clk_div", "vtp_clk_div"),

	DT_CLK(NULL, "usbphy_32khz_clkmux", "usbphy_32khz_clkmux"),

	DT_CLK("48300200.ehrpwm", "tbclk", "ehrpwm0_tbclk"),

	DT_CLK("48302200.ehrpwm", "tbclk", "ehrpwm1_tbclk"),

	DT_CLK("48304200.ehrpwm", "tbclk", "ehrpwm2_tbclk"),

	DT_CLK("48306200.ehrpwm", "tbclk", "ehrpwm3_tbclk"),

	DT_CLK("48308200.ehrpwm", "tbclk", "ehrpwm4_tbclk"),

	DT_CLK("4830a200.ehrpwm", "tbclk", "ehrpwm5_tbclk"),

	{ .node_name = NULL },

};