Merge branch 'for-rmk/740t' of git://git.kernel.org/pub/scm/linux/kernel/git/will/linux into fixes (4d855021) · Commits · e / devices / android_kernel_oneplus_sm7250

arch/arm/include/asm/glue-cache.h

+0 −8

Original line number	Original line	Diff line number	Diff line
	@@ -19,14 +19,6 @@
	#undef _CACHE		#undef _CACHE
	#undef MULTI_CACHE		#undef MULTI_CACHE

	#if defined(CONFIG_CPU_CACHE_V3)
	# ifdef _CACHE
	# define MULTI_CACHE 1
	# else
	# define _CACHE v3
	# endif
	#endif

	#if defined(CONFIG_CPU_CACHE_V4)		#if defined(CONFIG_CPU_CACHE_V4)
	# ifdef _CACHE		# ifdef _CACHE
	# define MULTI_CACHE 1		# define MULTI_CACHE 1

arch/arm/include/asm/tlbflush.h

+2 −9

Original line number	Original line	Diff line number	Diff line
	@@ -14,7 +14,6 @@

	#include <asm/glue.h>		#include <asm/glue.h>

	#define TLB_V3_PAGE (1 << 0)
	#define TLB_V4_U_PAGE (1 << 1)		#define TLB_V4_U_PAGE (1 << 1)
	#define TLB_V4_D_PAGE (1 << 2)		#define TLB_V4_D_PAGE (1 << 2)
	#define TLB_V4_I_PAGE (1 << 3)		#define TLB_V4_I_PAGE (1 << 3)
	@@ -22,7 +21,6 @@
	#define TLB_V6_D_PAGE (1 << 5)		#define TLB_V6_D_PAGE (1 << 5)
	#define TLB_V6_I_PAGE (1 << 6)		#define TLB_V6_I_PAGE (1 << 6)

	#define TLB_V3_FULL (1 << 8)
	#define TLB_V4_U_FULL (1 << 9)		#define TLB_V4_U_FULL (1 << 9)
	#define TLB_V4_D_FULL (1 << 10)		#define TLB_V4_D_FULL (1 << 10)
	#define TLB_V4_I_FULL (1 << 11)		#define TLB_V4_I_FULL (1 << 11)
	@@ -52,7 +50,6 @@
	* =============		* =============
	*		*
	* We have the following to choose from:		* We have the following to choose from:
	* v3 - ARMv3
	* v4 - ARMv4 without write buffer		* v4 - ARMv4 without write buffer
	* v4wb - ARMv4 with write buffer without I TLB flush entry instruction		* v4wb - ARMv4 with write buffer without I TLB flush entry instruction
	* v4wbi - ARMv4 with write buffer with I TLB flush entry instruction		* v4wbi - ARMv4 with write buffer with I TLB flush entry instruction
	@@ -330,7 +327,6 @@ static inline void local_flush_tlb_all(void)
	if (tlb_flag(TLB_WB))		if (tlb_flag(TLB_WB))
	dsb();		dsb();

	tlb_op(TLB_V3_FULL, "c6, c0, 0", zero);
	tlb_op(TLB_V4_U_FULL \| TLB_V6_U_FULL, "c8, c7, 0", zero);		tlb_op(TLB_V4_U_FULL \| TLB_V6_U_FULL, "c8, c7, 0", zero);
	tlb_op(TLB_V4_D_FULL \| TLB_V6_D_FULL, "c8, c6, 0", zero);		tlb_op(TLB_V4_D_FULL \| TLB_V6_D_FULL, "c8, c6, 0", zero);
	tlb_op(TLB_V4_I_FULL \| TLB_V6_I_FULL, "c8, c5, 0", zero);		tlb_op(TLB_V4_I_FULL \| TLB_V6_I_FULL, "c8, c5, 0", zero);
	@@ -351,9 +347,8 @@ static inline void local_flush_tlb_mm(struct mm_struct *mm)
	if (tlb_flag(TLB_WB))		if (tlb_flag(TLB_WB))
	dsb();		dsb();

	if (possible_tlb_flags & (TLB_V3_FULL\|TLB_V4_U_FULL\|TLB_V4_D_FULL\|TLB_V4_I_FULL)) {		if (possible_tlb_flags & (TLB_V4_U_FULL\|TLB_V4_D_FULL\|TLB_V4_I_FULL)) {
	if (cpumask_test_cpu(get_cpu(), mm_cpumask(mm))) {		if (cpumask_test_cpu(get_cpu(), mm_cpumask(mm))) {
	tlb_op(TLB_V3_FULL, "c6, c0, 0", zero);
	tlb_op(TLB_V4_U_FULL, "c8, c7, 0", zero);		tlb_op(TLB_V4_U_FULL, "c8, c7, 0", zero);
	tlb_op(TLB_V4_D_FULL, "c8, c6, 0", zero);		tlb_op(TLB_V4_D_FULL, "c8, c6, 0", zero);
	tlb_op(TLB_V4_I_FULL, "c8, c5, 0", zero);		tlb_op(TLB_V4_I_FULL, "c8, c5, 0", zero);
	@@ -385,9 +380,8 @@ local_flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)
	if (tlb_flag(TLB_WB))		if (tlb_flag(TLB_WB))
	dsb();		dsb();

	if (possible_tlb_flags & (TLB_V3_PAGE\|TLB_V4_U_PAGE\|TLB_V4_D_PAGE\|TLB_V4_I_PAGE\|TLB_V4_I_FULL) &&		if (possible_tlb_flags & (TLB_V4_U_PAGE\|TLB_V4_D_PAGE\|TLB_V4_I_PAGE\|TLB_V4_I_FULL) &&
	cpumask_test_cpu(smp_processor_id(), mm_cpumask(vma->vm_mm))) {		cpumask_test_cpu(smp_processor_id(), mm_cpumask(vma->vm_mm))) {
	tlb_op(TLB_V3_PAGE, "c6, c0, 0", uaddr);
	tlb_op(TLB_V4_U_PAGE, "c8, c7, 1", uaddr);		tlb_op(TLB_V4_U_PAGE, "c8, c7, 1", uaddr);
	tlb_op(TLB_V4_D_PAGE, "c8, c6, 1", uaddr);		tlb_op(TLB_V4_D_PAGE, "c8, c6, 1", uaddr);
	tlb_op(TLB_V4_I_PAGE, "c8, c5, 1", uaddr);		tlb_op(TLB_V4_I_PAGE, "c8, c5, 1", uaddr);
	@@ -418,7 +412,6 @@ static inline void local_flush_tlb_kernel_page(unsigned long kaddr)
	if (tlb_flag(TLB_WB))		if (tlb_flag(TLB_WB))
	dsb();		dsb();

	tlb_op(TLB_V3_PAGE, "c6, c0, 0", kaddr);
	tlb_op(TLB_V4_U_PAGE, "c8, c7, 1", kaddr);		tlb_op(TLB_V4_U_PAGE, "c8, c7, 1", kaddr);
	tlb_op(TLB_V4_D_PAGE, "c8, c6, 1", kaddr);		tlb_op(TLB_V4_D_PAGE, "c8, c6, 1", kaddr);
	tlb_op(TLB_V4_I_PAGE, "c8, c5, 1", kaddr);		tlb_op(TLB_V4_I_PAGE, "c8, c5, 1", kaddr);

arch/arm/mm/Kconfig

+1 −4

Original line number	Original line	Diff line number	Diff line
	@@ -43,7 +43,7 @@ config CPU_ARM740T
	depends on !MMU		depends on !MMU
	select CPU_32v4T		select CPU_32v4T
	select CPU_ABRT_LV4T		select CPU_ABRT_LV4T
	select CPU_CACHE_V3 # although the core is v4t		select CPU_CACHE_V4
	select CPU_CP15_MPU		select CPU_CP15_MPU
	select CPU_PABRT_LEGACY		select CPU_PABRT_LEGACY
	help		help
	@@ -469,9 +469,6 @@ config CPU_PABRT_V7
	bool		bool

	# The cache model		# The cache model
	config CPU_CACHE_V3
	bool

	config CPU_CACHE_V4		config CPU_CACHE_V4
	bool		bool

arch/arm/mm/Makefile

+0 −1

Original line number	Original line	Diff line number	Diff line
	@@ -33,7 +33,6 @@ obj-$(CONFIG_CPU_PABRT_LEGACY) += pabort-legacy.o
	obj-$(CONFIG_CPU_PABRT_V6) += pabort-v6.o		obj-$(CONFIG_CPU_PABRT_V6) += pabort-v6.o
	obj-$(CONFIG_CPU_PABRT_V7) += pabort-v7.o		obj-$(CONFIG_CPU_PABRT_V7) += pabort-v7.o

	obj-$(CONFIG_CPU_CACHE_V3) += cache-v3.o
	obj-$(CONFIG_CPU_CACHE_V4) += cache-v4.o		obj-$(CONFIG_CPU_CACHE_V4) += cache-v4.o
	obj-$(CONFIG_CPU_CACHE_V4WT) += cache-v4wt.o		obj-$(CONFIG_CPU_CACHE_V4WT) += cache-v4wt.o
	obj-$(CONFIG_CPU_CACHE_V4WB) += cache-v4wb.o		obj-$(CONFIG_CPU_CACHE_V4WB) += cache-v4wb.o

arch/arm/mm/cache-v3.S

deleted100644 → 0

+0 −137

Original line number	Original line	Diff line number	Diff line
	/*
	* linux/arch/arm/mm/cache-v3.S
	*
	* Copyright (C) 1997-2002 Russell king
	*
	* This program is free software; you can redistribute it and/or modify
	* it under the terms of the GNU General Public License version 2 as
	* published by the Free Software Foundation.
	*/
	#include <linux/linkage.h>
	#include <linux/init.h>
	#include <asm/page.h>
	#include "proc-macros.S"

	/*
	* flush_icache_all()
	*
	* Unconditionally clean and invalidate the entire icache.
	*/
	ENTRY(v3_flush_icache_all)
	mov pc, lr
	ENDPROC(v3_flush_icache_all)

	/*
	* flush_user_cache_all()
	*
	* Invalidate all cache entries in a particular address
	* space.
	*
	* - mm - mm_struct describing address space
	*/
	ENTRY(v3_flush_user_cache_all)
	/* FALLTHROUGH */
	/*
	* flush_kern_cache_all()
	*
	* Clean and invalidate the entire cache.
	*/
	ENTRY(v3_flush_kern_cache_all)
	/* FALLTHROUGH */

	/*
	* flush_user_cache_range(start, end, flags)
	*
	* Invalidate a range of cache entries in the specified
	* address space.
	*
	* - start - start address (may not be aligned)
	* - end - end address (exclusive, may not be aligned)
	* - flags - vma_area_struct flags describing address space
	*/
	ENTRY(v3_flush_user_cache_range)
	mov ip, #0
	mcreq p15, 0, ip, c7, c0, 0 @ flush ID cache
	mov pc, lr

	/*
	* coherent_kern_range(start, end)
	*
	* Ensure coherency between the Icache and the Dcache in the
	* region described by start. If you have non-snooping
	* Harvard caches, you need to implement this function.
	*
	* - start - virtual start address
	* - end - virtual end address
	*/
	ENTRY(v3_coherent_kern_range)
	/* FALLTHROUGH */

	/*
	* coherent_user_range(start, end)
	*
	* Ensure coherency between the Icache and the Dcache in the
	* region described by start. If you have non-snooping
	* Harvard caches, you need to implement this function.
	*
	* - start - virtual start address
	* - end - virtual end address
	*/
	ENTRY(v3_coherent_user_range)
	mov r0, #0
	mov pc, lr

	/*
	* flush_kern_dcache_area(void *page, size_t size)
	*
	* Ensure no D cache aliasing occurs, either with itself or
	* the I cache
	*
	* - addr - kernel address
	* - size - region size
	*/
	ENTRY(v3_flush_kern_dcache_area)
	/* FALLTHROUGH */

	/*
	* dma_flush_range(start, end)
	*
	* Clean and invalidate the specified virtual address range.
	*
	* - start - virtual start address
	* - end - virtual end address
	*/
	ENTRY(v3_dma_flush_range)
	mov r0, #0
	mcr p15, 0, r0, c7, c0, 0 @ flush ID cache
	mov pc, lr

	/*
	* dma_unmap_area(start, size, dir)
	* - start - kernel virtual start address
	* - size - size of region
	* - dir - DMA direction
	*/
	ENTRY(v3_dma_unmap_area)
	teq r2, #DMA_TO_DEVICE
	bne v3_dma_flush_range
	/* FALLTHROUGH */

	/*
	* dma_map_area(start, size, dir)
	* - start - kernel virtual start address
	* - size - size of region
	* - dir - DMA direction
	*/
	ENTRY(v3_dma_map_area)
	mov pc, lr
	ENDPROC(v3_dma_unmap_area)
	ENDPROC(v3_dma_map_area)

	.globl v3_flush_kern_cache_louis
	.equ v3_flush_kern_cache_louis, v3_flush_kern_cache_all

	__INITDATA

	@ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
	define_cache_functions v3