Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 4d78c8dc authored by Arun Siluvery's avatar Arun Siluvery Committed by Daniel Vetter
Browse files

drm/i915: Fix warnings reported by 0-day 



Kernel 0-day framework reported warnings with WA batch patches, this patch
fixes those warnings and an additional warning reported in intel_lrc.c file.

Signed-off-by: default avatarArun Siluvery <arun.siluvery@linux.intel.com>
Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent a5ac0f90

drivers/gpu/drm/i915/intel_lrc.c

+3 −1
Original line number Diff line number Diff line
@@ -784,6 +784,7 @@ static int logical_ring_prepare(struct drm_i915_gem_request *req, int bytes) 
 * intel_logical_ring_begin() - prepare the logical ringbuffer to accept some commands

 *

 * @request: The request to start some new work for

 * @ctx: Logical ring context whose ringbuffer is being prepared.

 * @num_dwords: number of DWORDs that we plan to write to the ringbuffer.

 *

 * The ringbuffer might not be ready to accept the commands right away (maybe it needs to
@@ -1132,7 +1133,7 @@ static inline int wa_ctx_end(struct i915_wa_ctx_bb *wa_ctx, 
 *

 *  The number of WA applied are not known at the beginning; we use this field

 *  to return the no of DWORDS written.



 *

 *  It is to be noted that this batch does not contain MI_BATCH_BUFFER_END

 *  so it adds NOOPs as padding to make it cacheline aligned.

 *  MI_BATCH_BUFFER_END will be added to perctx batch and both of them together
@@ -1194,6 +1195,7 @@ static int gen8_init_indirectctx_bb(struct intel_engine_cs *ring, 
 * @wa_ctx: structure representing wa_ctx

 *  offset: specifies start of the batch, should be cache-aligned.

 *  size: size of the batch in DWORDS but HW expects in terms of cachelines

 * @batch: page in which WA are loaded

 * @offset: This field specifies the start of this batch.

 *   This batch is started immediately after indirect_ctx batch. Since we ensure

 *   that indirect_ctx ends on a cacheline this batch is aligned automatically.