Merge "ARM: dts: msm: Add NPU support for lagoon" (4c64f90e) · Commits · e / devices / android_kernel_oneplus_sm7250

qcom/lagoon-npu.dtsi

0 → 100644

+145 −0

Original line number	Diff line number	Diff line
		&soc {
		msm_npu: qcom,msm_npu@9800000 {
		compatible = "qcom,msm-npu";
		status = "ok";
		reg = <0x9900000 0x20000>,
		<0x99F0000 0x10000>,
		<0x9980000 0x10000>,
		<0x17c00000 0x10000>,
		<0x01F40000 0x40000>;
		reg-names = "tcm", "core", "cc", "apss_shared", "tcsr";
		interrupts = <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>,
		<GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
		<GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
		<GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "error_irq", "wdg_bite_irq", "ipc_irq",
		"general_irq";

		clocks = <&npucc NPU_CC_XO_CLK>,
		<&npucc NPU_CC_CORE_CLK>,
		<&npucc NPU_CC_CAL_HM0_CLK>,
		<&npucc NPU_CC_CAL_HM0_CDC_CLK>,
		<&npucc NPU_CC_NOC_AXI_CLK>,
		<&npucc NPU_CC_NOC_AHB_CLK>,
		<&npucc NPU_CC_NOC_DMA_CLK>,
		<&npucc NPU_CC_RSC_XO_CLK>,
		<&npucc NPU_CC_S2P_CLK>,
		<&npucc NPU_CC_BWMON_CLK>,
		<&npucc NPU_CC_CAL_HM0_PERF_CNT_CLK>,
		<&npucc NPU_CC_BTO_CORE_CLK>,
		<&npucc NPU_DSP_CORE_CLK_SRC>;
		clock-names = "xo_clk",
		"npu_core_clk",
		"cal_hm0_clk",
		"cal_hm0_cdc_clk",
		"axi_clk",
		"ahb_clk",
		"dma_clk",
		"rsc_xo_clk",
		"s2p_clk",
		"bwmon_clk",
		"cal_hm0_perf_cnt_clk",
		"bto_core_clk",
		"dsp_core_clk_src";

		vdd-supply = <&npu_cc_core_gdsc>;
		vdd_cx-supply = <&VDD_CX_LEVEL>;
		qcom,proxy-reg-names ="vdd", "vdd_cx";
		#cooling-cells = <2>;
		qcom,npu-pwrlevels {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "qcom,npu-pwrlevels";
		initial-pwrlevel = <4>;
		qcom,npu-pwrlevel@0 {
		reg = <0>;
		vreg = <1>;
		clk-freq = <19200000
		100000000
		200000000
		268000000
		150000000
		30000000
		200000000
		19200000
		50000000
		19200000
		268000000
		19200000
		300000000>;
		};

		qcom,npu-pwrlevel@1 {
		reg = <1>;
		vreg = <2>;
		clk-freq = <19200000
		200000000
		400000000
		403000000
		200000000
		37500000
		300000000
		19200000
		50000000
		19200000
		403000000
		19200000
		400000000>;
		};

		qcom,npu-pwrlevel@2 {
		reg = <2>;
		vreg = <3>;
		clk-freq = <19200000
		333000000
		515000000
		515000000
		300000000
		37500000
		403000000
		19200000
		50000000
		19200000
		515000000
		19200000
		500000000>;
		};

		qcom,npu-pwrlevel@3 {
		reg = <3>;
		vreg = <4>;
		clk-freq = <19200000
		428000000
		650000000
		650000000
		403000000
		75000000
		600000000
		19200000
		100000000
		19200000
		650000000
		19200000
		660000000>;
		};

		qcom,npu-pwrlevel@4 {
		reg = <4>;
		vreg = <6>;
		clk-freq = <19200000
		500000000
		800000000
		850000000
		533000000
		75000000
		710000000
		19200000
		100000000
		19200000
		850000000
		19200000
		800000000>;
		};
		};
		};
		};

qcom/lagoon.dtsi

+15 −1

Original line number	Diff line number	Diff line
		@@ -395,7 +395,7 @@
		reg = <0x0 0x86000000 0x0 0x500000>;
		};

		npu_mem: npu_region@86500000 {
		pil_npu_mem: pil_npu_region@86500000 {
		compatible = "removed-dma-pool";
		no-map;
		reg = <0x0 0x86500000 0x0 0x500000>;
		@@ -1522,10 +1522,24 @@
		qcom,firmware-name = "venus";
		memory-region = <&pil_video_mem>;
		};

		qcom,npu@9800000 {
		compatible = "qcom,pil-tz-generic";
		reg = <0x9800000 0x800000>;
		status = "ok";
		qcom,pas-id = <23>;
		qcom,firmware-name = "npu";
		memory-region = <&pil_npu_mem>;

		/* Outputs to npu */
		qcom,smem-states = <&npu_smp2p_out 0>;
		qcom,smem-state-names = "qcom,force-stop";
		};
		};

		#include "lagoon-gdsc.dtsi"
		#include "lagoon-usb.dtsi"
		#include "lagoon-npu.dtsi"

		&gcc_pcie_0_gdsc {
		qcom,support-hw-trigger;