Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 4bdce781 authored by Marijn Suijten's avatar Marijn Suijten Committed by Greg Kroah-Hartman
Browse files

drm/msm/mdp5: Configure PP_SYNC_HEIGHT to double the vtotal 



[ Upstream commit 2ad52bdb220de5ab348098e3482b01235d15a842 ]

Leaving this at a close-to-maximum register value 0xFFF0 means it takes
very long for the MDSS to generate a software vsync interrupt when the
hardware TE interrupt doesn't arrive.  Configuring this to double the
vtotal (like some downstream kernels) leads to a frame to take at most
twice before the vsync signal, until hardware TE comes up.

In this case the hardware interrupt responsible for providing this
signal - "disp-te" gpio - is not hooked up to the mdp5 vsync/pp logic at
all.  This solves severe panel update issues observed on at least the
Xperia Loire and Tone series, until said gpio is properly hooked up to
an irq.

Suggested-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Signed-off-by: default avatarMarijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Link: https://lore.kernel.org/r/20210406214726.131534-2-marijn.suijten@somainline.org


Signed-off-by: default avatarRob Clark <robdclark@chromium.org>
Signed-off-by: default avatarSasha Levin <sashal@kernel.org>
parent a30d538c

drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c

+9 −1
Original line number Diff line number Diff line
@@ -78,9 +78,17 @@ static int pingpong_tearcheck_setup(struct drm_encoder *encoder, 
		| MDP5_PP_SYNC_CONFIG_VSYNC_IN_EN;

	cfg |= MDP5_PP_SYNC_CONFIG_VSYNC_COUNT(vclks_line);



	/*

	 * Tearcheck emits a blanking signal every vclks_line * vtotal * 2 ticks on

	 * the vsync_clk equating to roughly half the desired panel refresh rate.

	 * This is only necessary as stability fallback if interrupts from the

	 * panel arrive too late or not at all, but is currently used by default

	 * because these panel interrupts are not wired up yet.

	 */

	mdp5_write(mdp5_kms, REG_MDP5_PP_SYNC_CONFIG_VSYNC(pp_id), cfg);

	mdp5_write(mdp5_kms,

		REG_MDP5_PP_SYNC_CONFIG_HEIGHT(pp_id), 0xfff0);

		REG_MDP5_PP_SYNC_CONFIG_HEIGHT(pp_id), (2 * mode->vtotal));



	mdp5_write(mdp5_kms,

		REG_MDP5_PP_VSYNC_INIT_VAL(pp_id), mode->vdisplay);

	mdp5_write(mdp5_kms, REG_MDP5_PP_RD_PTR_IRQ(pp_id), mode->vdisplay + 1);