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Commit 4b914286 authored by Christophe Leroy's avatar Christophe Leroy Committed by Scott Wood
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powerpc/8xx: Implement support of hugepages 



8xx uses a two level page table with two different linux page size
support (4k and 16k). 8xx also support two different hugepage sizes
512k and 8M. In order to support them on linux we define two different
page table layout.

The size of pages is in the PGD entry, using PS field (bits 28-29):
00 : Small pages (4k or 16k)
01 : 512k pages
10 : reserved
11 : 8M pages

For 512K hugepage size a pgd entry have the below format
[<hugepte address >0101] . The hugepte table allocated will contain 8
entries pointing to 512K huge pte in 4k pages mode and 64 entries in
16k pages mode.

For 8M in 16k mode, a pgd entry have the below format
[<hugepte address >1101] . The hugepte table allocated will contain 8
entries pointing to 8M huge pte.

For 8M in 4k mode, multiple pgd entries point to the same hugepte
address and pgd entry will have the below format
[<hugepte address>1101]. The hugepte table allocated will only have one
entry.

For the time being, we do not support CPU15 ERRATA when HUGETLB is
selected

Signed-off-by: default avatarChristophe Leroy <christophe.leroy@c-s.fr>
Reviewed-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> (v3, for the generic bits)
Signed-off-by: default avatarScott Wood <oss@buserror.net>
parent 03bb2d65

arch/powerpc/include/asm/hugetlb.h

+18 −1
Original line number Diff line number Diff line
@@ -51,12 +51,20 @@ static inline void __local_flush_hugetlb_page(struct vm_area_struct *vma, 
static inline pte_t *hugepd_page(hugepd_t hpd)

{

	BUG_ON(!hugepd_ok(hpd));

#ifdef CONFIG_PPC_8xx

	return (pte_t *)__va(hpd.pd & ~(_PMD_PAGE_MASK | _PMD_PRESENT_MASK));

#else

	return (pte_t *)((hpd.pd & ~HUGEPD_SHIFT_MASK) | PD_HUGE);

#endif

}



static inline unsigned int hugepd_shift(hugepd_t hpd)

{

#ifdef CONFIG_PPC_8xx

	return ((hpd.pd & _PMD_PAGE_MASK) >> 1) + 17;

#else

	return hpd.pd & HUGEPD_SHIFT_MASK;

#endif

}



#endif /* CONFIG_PPC_BOOK3S_64 */
@@ -99,7 +107,15 @@ static inline int is_hugepage_only_range(struct mm_struct *mm, 


void book3e_hugetlb_preload(struct vm_area_struct *vma, unsigned long ea,

			    pte_t pte);

#ifdef CONFIG_PPC_8xx

static inline void flush_hugetlb_page(struct vm_area_struct *vma,

				      unsigned long vmaddr)

{

	flush_tlb_page(vma, vmaddr);

}

#else

void flush_hugetlb_page(struct vm_area_struct *vma, unsigned long vmaddr);

#endif



void hugetlb_free_pgd_range(struct mmu_gather *tlb, unsigned long addr,

			    unsigned long end, unsigned long floor,
@@ -205,7 +221,8 @@ static inline pte_t *hugepte_offset(hugepd_t hpd, unsigned long addr, 
 * are reserved early in the boot process by memblock instead of via

 * the .dts as on IBM platforms.

 */

#if defined(CONFIG_HUGETLB_PAGE) && defined(CONFIG_PPC_FSL_BOOK3E)

#if defined(CONFIG_HUGETLB_PAGE) && (defined(CONFIG_PPC_FSL_BOOK3E) || \

    defined(CONFIG_PPC_8xx))

extern void __init reserve_hugetlb_gpages(void);

#else

static inline void reserve_hugetlb_gpages(void)

arch/powerpc/include/asm/mmu-8xx.h

+35 −0
Original line number Diff line number Diff line
@@ -172,6 +172,41 @@ typedef struct { 


#define PHYS_IMMR_BASE (mfspr(SPRN_IMMR) & 0xfff80000)

#define VIRT_IMMR_BASE (__fix_to_virt(FIX_IMMR_BASE))



/* Page size definitions, common between 32 and 64-bit

 *

 *    shift : is the "PAGE_SHIFT" value for that page size

 *    penc  : is the pte encoding mask

 *

 */

struct mmu_psize_def {

	unsigned int	shift;	/* number of bits */

	unsigned int	enc;	/* PTE encoding */

	unsigned int    ind;    /* Corresponding indirect page size shift */

	unsigned int	flags;

#define MMU_PAGE_SIZE_DIRECT	0x1	/* Supported as a direct size */

#define MMU_PAGE_SIZE_INDIRECT	0x2	/* Supported as an indirect size */

};



extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];



static inline int shift_to_mmu_psize(unsigned int shift)

{

	int psize;



	for (psize = 0; psize < MMU_PAGE_COUNT; ++psize)

		if (mmu_psize_defs[psize].shift == shift)

			return psize;

	return -1;

}



static inline unsigned int mmu_psize_to_shift(unsigned int mmu_psize)

{

	if (mmu_psize_defs[mmu_psize].shift)

		return mmu_psize_defs[mmu_psize].shift;

	BUG();

}



#endif /* !__ASSEMBLY__ */



#if defined(CONFIG_PPC_4K_PAGES)

arch/powerpc/include/asm/mmu.h

+12 −11
Original line number Diff line number Diff line
@@ -264,19 +264,20 @@ static inline bool early_radix_enabled(void) 
#define MMU_PAGE_64K	2

#define MMU_PAGE_64K_AP	3	/* "Admixed pages" (hash64 only) */

#define MMU_PAGE_256K	4

#define MMU_PAGE_1M	5

#define MMU_PAGE_2M	6

#define MMU_PAGE_4M	7

#define MMU_PAGE_8M	8

#define MMU_PAGE_16M	9

#define MMU_PAGE_64M	10

#define MMU_PAGE_256M	11

#define MMU_PAGE_1G	12

#define MMU_PAGE_16G	13

#define MMU_PAGE_64G	14

#define MMU_PAGE_512K	5

#define MMU_PAGE_1M	6

#define MMU_PAGE_2M	7

#define MMU_PAGE_4M	8

#define MMU_PAGE_8M	9

#define MMU_PAGE_16M	10

#define MMU_PAGE_64M	11

#define MMU_PAGE_256M	12

#define MMU_PAGE_1G	13

#define MMU_PAGE_16G	14

#define MMU_PAGE_64G	15



/* N.B. we need to change the type of hpte_page_sizes if this gets to be > 16 */

#define MMU_PAGE_COUNT	15

#define MMU_PAGE_COUNT	16



#ifdef CONFIG_PPC_BOOK3S_64

#include <asm/book3s/64/mmu.h>

arch/powerpc/include/asm/nohash/32/pte-8xx.h

+1 −0
Original line number Diff line number Diff line
@@ -49,6 +49,7 @@ 
#define _PMD_BAD	0x0ff0

#define _PMD_PAGE_MASK	0x000c

#define _PMD_PAGE_8M	0x000c

#define _PMD_PAGE_512K	0x0004



/* Until my rework is finished, 8xx still needs atomic PTE updates */

#define PTE_ATOMIC_UPDATES	1

arch/powerpc/include/asm/nohash/pgtable.h

+4 −0
Original line number Diff line number Diff line
@@ -226,7 +226,11 @@ extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, 
#ifdef CONFIG_HUGETLB_PAGE

static inline int hugepd_ok(hugepd_t hpd)

{

#ifdef CONFIG_PPC_8xx

	return ((hpd.pd & 0x4) != 0);

#else

	return (hpd.pd > 0);

#endif

}



static inline int pmd_huge(pmd_t pmd)