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Commit 4b6cd64e authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915: Kill off dead code from skl_dpll0_enable() 



We calculate the CDCLK_CTL value from scratch so no need to attempt
some form of RMW first.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1462995892-32416-10-git-send-email-ville.syrjala@linux.intel.com


Reviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
parent 430e05de

drivers/gpu/drm/i915/intel_display.c

+0 −5
Original line number Original line Diff line number Diff line
@@ -5562,17 +5562,12 @@ skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco) 
	u32 val;

	u32 val;





	/* select the minimum CDCLK before enabling DPLL 0 */

	/* select the minimum CDCLK before enabling DPLL 0 */

	val = I915_READ(CDCLK_CTL);

	val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;

	val |= CDCLK_FREQ_337_308;



	if (required_vco == 8640)

	if (required_vco == 8640)

		min_freq = 308570;

		min_freq = 308570;

	else

	else

		min_freq = 337500;

		min_freq = 337500;





	val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);

	val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);



	I915_WRITE(CDCLK_CTL, val);

	I915_WRITE(CDCLK_CTL, val);

	POSTING_READ(CDCLK_CTL);

	POSTING_READ(CDCLK_CTL);