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Commit 4b394a23 authored by Gary R Hook's avatar Gary R Hook Committed by Herbert Xu
Browse files

crypto: ccp - Let a v5 CCP provide the same function as v3 



Enable equivalent function on a v5 CCP. Add support for a
version 5 CCP which enables AES/XTS/SHA services. Also,
more work on the data structures to virtualize
functionality.

Signed-off-by: default avatarGary R Hook <gary.hook@amd.com>
Signed-off-by: default avatarHerbert Xu <herbert@gondor.apana.org.au>
parent bb4e89b3

drivers/crypto/ccp/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -2,6 +2,7 @@ obj-$(CONFIG_CRYPTO_DEV_CCP_DD) += ccp.o 
ccp-objs := ccp-dev.o \

	    ccp-ops.o \

	    ccp-dev-v3.o \

	    ccp-dev-v5.o \

	    ccp-platform.o \

	    ccp-dmaengine.o

ccp-$(CONFIG_PCI) += ccp-pci.o

drivers/crypto/ccp/ccp-crypto-sha.c

+17 −1
Original line number Diff line number Diff line
@@ -4,6 +4,7 @@ 
 * Copyright (C) 2013,2016 Advanced Micro Devices, Inc.

 *

 * Author: Tom Lendacky <thomas.lendacky@amd.com>

 * Author: Gary R Hook <gary.hook@amd.com>

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as
@@ -134,7 +135,22 @@ static int ccp_do_sha_update(struct ahash_request *req, unsigned int nbytes, 
	rctx->cmd.engine = CCP_ENGINE_SHA;

	rctx->cmd.u.sha.type = rctx->type;

	rctx->cmd.u.sha.ctx = &rctx->ctx_sg;

	rctx->cmd.u.sha.ctx_len = sizeof(rctx->ctx);



	switch (rctx->type) {

	case CCP_SHA_TYPE_1:

		rctx->cmd.u.sha.ctx_len = SHA1_DIGEST_SIZE;

		break;

	case CCP_SHA_TYPE_224:

		rctx->cmd.u.sha.ctx_len = SHA224_DIGEST_SIZE;

		break;

	case CCP_SHA_TYPE_256:

		rctx->cmd.u.sha.ctx_len = SHA256_DIGEST_SIZE;

		break;

	default:

		/* Should never get here */

		break;

	}



	rctx->cmd.u.sha.src = sg;

	rctx->cmd.u.sha.src_len = rctx->hash_cnt;

	rctx->cmd.u.sha.opad = ctx->u.sha.key_len ?

drivers/crypto/ccp/ccp-dev-v3.c

+16 −12
Original line number Diff line number Diff line
@@ -405,6 +405,7 @@ static int ccp_init(struct ccp_device *ccp) 
	init_waitqueue_head(&ccp->sb_queue);

	init_waitqueue_head(&ccp->suspend_queue);



	dev_dbg(dev, "Starting threads...\n");

	/* Create a kthread for each queue */

	for (i = 0; i < ccp->cmd_q_count; i++) {

		struct task_struct *kthread;
@@ -424,6 +425,13 @@ static int ccp_init(struct ccp_device *ccp) 
		wake_up_process(kthread);

	}



	dev_dbg(dev, "Enabling interrupts...\n");

	/* Enable interrupts */

	iowrite32(qim, ccp->io_regs + IRQ_MASK_REG);



	dev_dbg(dev, "Registering device...\n");

	ccp_add_device(ccp);



	/* Register the RNG */

	ccp->hwrng.name = ccp->rngname;

	ccp->hwrng.read = ccp_trng_read;
@@ -438,11 +446,6 @@ static int ccp_init(struct ccp_device *ccp) 
	if (ret)

		goto e_hwrng;



	ccp_add_device(ccp);



	/* Enable interrupts */

	iowrite32(qim, ccp->io_regs + IRQ_MASK_REG);



	return 0;



e_hwrng:
@@ -468,7 +471,13 @@ static void ccp_destroy(struct ccp_device *ccp) 
	struct ccp_cmd *cmd;

	unsigned int qim, i;



	/* Remove this device from the list of available units first */

	/* Unregister the DMA engine */

	ccp_dmaengine_unregister(ccp);



	/* Unregister the RNG */

	hwrng_unregister(&ccp->hwrng);



	/* Remove this device from the list of available units */

	ccp_del_device(ccp);



	/* Build queue interrupt mask (two interrupt masks per queue) */
@@ -488,12 +497,6 @@ static void ccp_destroy(struct ccp_device *ccp) 
	}

	iowrite32(qim, ccp->io_regs + IRQ_STATUS_REG);



	/* Unregister the DMA engine */

	ccp_dmaengine_unregister(ccp);



	/* Unregister the RNG */

	hwrng_unregister(&ccp->hwrng);



	/* Stop the queue kthreads */

	for (i = 0; i < ccp->cmd_q_count; i++)

		if (ccp->cmd_q[i].kthread)
@@ -570,6 +573,7 @@ static const struct ccp_actions ccp3_actions = { 


struct ccp_vdata ccpv3 = {

	.version = CCP_VERSION(3, 0),

	.setup = NULL,

	.perform = &ccp3_actions,

	.bar = 2,

	.offset = 0x20000,