Merge b46a5e274aaa39642d8133285acdc1d86b1f049a on remote branch (4b166416) · Commits · e / devices / android_kernel_oneplus_sm7250

drivers/clk/qcom/gpucc-bengal.c

+2 −1

Original line number	Diff line number	Diff line
		@@ -364,12 +364,13 @@ static struct clk_branch gpu_cc_cxo_clk = {

		static struct clk_branch gpu_cc_gx_cxo_clk = {
		.halt_reg = 0x1060,
		.halt_check = BRANCH_HALT,
		.halt_check = BRANCH_HALT_DELAY,
		.clkr = {
		.enable_reg = 0x1060,
		.enable_mask = BIT(0),
		.hw.init = &(struct clk_init_data){
		.name = "gpu_cc_gx_cxo_clk",
		.flags = CLK_IS_CRITICAL,
		.ops = &clk_branch2_ops,
		},
		},

drivers/esoc/esoc-mdm-4x.c

+1 −16

Original line number	Diff line number	Diff line
		@@ -1081,27 +1081,12 @@ static int sdx55m_setup_hw(struct mdm_ctrl *mdm,
		dev_err(mdm->dev, "Failed to parse DT gpios\n");
		goto err_destroy_wrkq;
		}
		if (!of_property_read_bool(node, "qcom,esoc-spmi-soft-reset")) {
		ret = mdm_pon_dt_init(mdm);
		if (ret) {
		esoc_mdm_log("Failed to parse PON DT gpios\n");
		dev_err(mdm->dev, "Failed to parse PON DT gpio\n");
		goto err_destroy_wrkq;
		}

		ret = mdm_pon_setup(mdm);
		if (ret) {
		esoc_mdm_log("Failed to setup PON\n");
		dev_err(mdm->dev, "Failed to setup PON\n");
		goto err_destroy_wrkq;
		}
		}

		ret = mdm_pinctrl_init(mdm);
		if (ret) {
		esoc_mdm_log("Failed to init pinctrl\n");
		dev_err(mdm->dev, "Failed to init pinctrl\n");
		goto err_release_ipc;
		goto err_destroy_wrkq;
		}

		ret = mdm_configure_ipc(mdm, pdev);

drivers/esoc/esoc-mdm-pon.c

+7 −43

Original line number	Diff line number	Diff line
		@@ -74,12 +74,8 @@ static int sdx50m_toggle_soft_reset(struct mdm_ctrl *mdm, bool atomic)
		/* This function can be called from atomic context. */
		static int sdx55m_toggle_soft_reset(struct mdm_ctrl *mdm, bool atomic)
		{
		struct device_node *node = mdm->dev->of_node;
		int rc;
		int soft_reset_direction_assert = 0,
		soft_reset_direction_de_assert = 1;

		if (of_property_read_bool(node, "qcom,esoc-spmi-soft-reset")) {
		esoc_mdm_log("Doing a Warm reset using SPMI\n");
		rc = qpnp_pon_modem_pwr_off(PON_POWER_OFF_WARM_RESET);
		if (rc) {
		@@ -91,36 +87,6 @@ static int sdx55m_toggle_soft_reset(struct mdm_ctrl *mdm, bool atomic)
		return 0;
		}

		if (mdm->soft_reset_inverted) {
		soft_reset_direction_assert = 1;
		soft_reset_direction_de_assert = 0;
		}

		esoc_mdm_log("RESET GPIO value (before doing a reset): %d\n",
		gpio_get_value(MDM_GPIO(mdm, AP2MDM_SOFT_RESET)));
		esoc_mdm_log("Setting AP2MDM_SOFT_RESET = %d\n",
		soft_reset_direction_assert);
		gpio_direction_output(MDM_GPIO(mdm, AP2MDM_SOFT_RESET),
		soft_reset_direction_assert);
		/*
		* Allow PS hold assert to be detected
		*/
		if (!atomic)
		usleep_range(80000, 180000);
		else
		/*
		* The flow falls through this path as a part of the
		* panic handler, which has to executed atomically.
		*/
		mdelay(100);

		esoc_mdm_log("Setting AP2MDM_SOFT_RESET = %d\n",
		soft_reset_direction_de_assert);
		gpio_direction_output(MDM_GPIO(mdm, AP2MDM_SOFT_RESET),
		soft_reset_direction_de_assert);
		return 0;
		}

		static int mdm4x_do_first_power_on(struct mdm_ctrl *mdm)
		{
		int i;
		@@ -325,6 +291,4 @@ struct mdm_pon_ops sdx55m_pon_ops = {
		.pon = mdm4x_do_first_power_on,
		.soft_reset = sdx55m_toggle_soft_reset,
		.poff_force = sdx55m_power_down,
		.dt_init = mdm4x_pon_dt_init,
		.setup = mdm4x_pon_setup,
		};

drivers/gpu/msm/adreno_snapshot.c

+11 −15

Original line number	Diff line number	Diff line
		@@ -276,19 +276,15 @@ static void snapshot_rb_ibs(struct kgsl_device *device,
		struct kgsl_snapshot *snapshot)
		{
		struct adreno_device *adreno_dev = ADRENO_DEVICE(device);
		unsigned int rptr, *rbptr;
		unsigned int *rbptr, rptr = adreno_get_rptr(rb);
		int index, i;
		int parse_ibs = 0, ib_parse_start;

		/* Get the current read pointers for the RB */
		adreno_readreg(adreno_dev, ADRENO_REG_CP_RB_RPTR, &rptr);

		/*
		* Figure out the window of ringbuffer data to dump. First we need to
		* find where the last processed IB ws submitted. Start walking back
		* from the rptr
		*/

		index = rptr;
		rbptr = rb->buffer_desc.hostptr;

		@@ -848,19 +844,19 @@ void adreno_snapshot(struct kgsl_device device, struct kgsl_snapshot snapshot,
		if (gpudev->snapshot)
		gpudev->snapshot(adreno_dev, snapshot);

		/* Dumping these buffers is useless if the GX is not on */
		if (!gmu_core_dev_gx_is_on(device))
		return;

		setup_fault_process(device, snapshot,
		context ? context->proc_priv : NULL);

		if (gmu_core_dev_gx_is_on(device)) {
		adreno_readreg64(adreno_dev, ADRENO_REG_CP_IB1_BASE,
		ADRENO_REG_CP_IB1_BASE_HI, &snapshot->ib1base);
		adreno_readreg(adreno_dev, ADRENO_REG_CP_IB1_BUFSZ, &snapshot->ib1size);
		adreno_readreg(adreno_dev, ADRENO_REG_CP_IB1_BUFSZ,
		&snapshot->ib1size);
		adreno_readreg64(adreno_dev, ADRENO_REG_CP_IB2_BASE,
		ADRENO_REG_CP_IB2_BASE_HI, &snapshot->ib2base);
		adreno_readreg(adreno_dev, ADRENO_REG_CP_IB2_BUFSZ, &snapshot->ib2size);
		adreno_readreg(adreno_dev, ADRENO_REG_CP_IB2_BUFSZ,
		&snapshot->ib2size);
		}

		snapshot->ib1dumped = false;
		snapshot->ib2dumped = false;

drivers/thermal/qcom/adc-tm5.c

+23 −2

Original line number	Diff line number	Diff line
		@@ -209,9 +209,30 @@ static int adc_tm5_configure(struct adc_tm_sensor *sensor,
		buf[7] \|= ADC_TM_Mn_MEAS_EN;

		ret = adc_tm5_write_reg(chip,
		ADC_TM_Mn_ADC_CH_SEL_CTL(btm_chan_idx), buf, 8);
		ADC_TM_Mn_ADC_CH_SEL_CTL(btm_chan_idx), buf, 1);
		if (ret < 0) {
		pr_err("adc-tm block write failed with %d\n", ret);
		pr_err("adc-tm channel select failed\n");
		return ret;
		}

		ret = adc_tm5_write_reg(chip,
		ADC_TM_Mn_MEAS_INTERVAL_CTL(btm_chan_idx), &buf[5], 1);
		if (ret < 0) {
		pr_err("adc-tm timer select failed\n");
		return ret;
		}

		ret = adc_tm5_write_reg(chip,
		ADC_TM_Mn_CTL(btm_chan_idx), &buf[6], 1);
		if (ret < 0) {
		pr_err("adc-tm parameter select failed\n");
		return ret;
		}

		ret = adc_tm5_write_reg(chip,
		ADC_TM_Mn_EN(btm_chan_idx), &buf[7], 1);
		if (ret < 0) {
		pr_err("adc-tm monitoring enable failed\n");
		return ret;
		}