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Commit 4a5a2711 authored by Martin Blumenstingl's avatar Martin Blumenstingl Committed by Kevin Hilman
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ARM: dts: meson8: add support for booting the secondary CPU cores 



Booting the secondary CPU cores involves the following nodes/devices:
- SCU (Snoop-Control-Unit, for which we already have a DT node)
- a reset line for each CPU core, provided by the reset-controller
  which is built into the clock-controller
- the PMU (power management unit) which controls the power of the CPU
  cores
- a range in the SRAM specifically reserved for booting secondary CPU
  cores
- the "enable-method" which activates booting the secondary CPU cores

This adds all required nodes and properties to boot the secondary CPU
cores.

Suggested-by: default avatarCarlo Caione <carlo@caione.org>
Signed-off-by: default avatarMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: default avatarKevin Hilman <khilman@baylibre.com>
parent 88b1b18f

arch/arm/boot/dts/meson8.dtsi

+21 −0
Original line number Diff line number Diff line
@@ -45,6 +45,7 @@ 


#include <dt-bindings/clock/meson8b-clkc.h>

#include <dt-bindings/gpio/meson8-gpio.h>

#include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>

#include "meson.dtsi"



/ {
@@ -60,6 +61,8 @@ 
			compatible = "arm,cortex-a9";

			next-level-cache = <&L2>;

			reg = <0x200>;

			enable-method = "amlogic,meson8-smp";

			resets = <&clkc CLKC_RESET_CPU0_SOFT_RESET>;

		};



		cpu@201 {
@@ -67,6 +70,8 @@ 
			compatible = "arm,cortex-a9";

			next-level-cache = <&L2>;

			reg = <0x201>;

			enable-method = "amlogic,meson8-smp";

			resets = <&clkc CLKC_RESET_CPU1_SOFT_RESET>;

		};



		cpu@202 {
@@ -74,6 +79,8 @@ 
			compatible = "arm,cortex-a9";

			next-level-cache = <&L2>;

			reg = <0x202>;

			enable-method = "amlogic,meson8-smp";

			resets = <&clkc CLKC_RESET_CPU2_SOFT_RESET>;

		};



		cpu@203 {
@@ -81,6 +88,8 @@ 
			compatible = "arm,cortex-a9";

			next-level-cache = <&L2>;

			reg = <0x203>;

			enable-method = "amlogic,meson8-smp";

			resets = <&clkc CLKC_RESET_CPU3_SOFT_RESET>;

		};

	};
@@ -118,6 +127,11 @@ 
}; /* end of / */



&aobus {

	pmu: pmu@e0 {

		compatible = "amlogic,meson8-pmu", "syscon";

		reg = <0xe0 0x8>;

	};



	pinctrl_aobus: pinctrl@84 {

		compatible = "amlogic,meson8-aobus-pinctrl";

		reg = <0x84 0xc>;
@@ -254,6 +268,13 @@ 
	};

};



&ahb_sram {

	smp-sram@1ff80 {

		compatible = "amlogic,meson8-smp-sram";

		reg = <0x1ff80 0x8>;

	};

};



&ethmac {

	clocks = <&clkc CLKID_ETH>;

	clock-names = "stmmaceth";