Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 4a49fbb6 authored by Venkat Chinta's avatar Venkat Chinta Committed by Gerrit - the friendly Code Review server
Browse files

msm: camera: vfe: Update register programming 



VFE Bus 2.0 client configuration register requires setting
the sixteenth bit instead of the first bit as earlier. Bus
2.0 cgc override register now holds more bits to account
for the increased number of clients. VFE core must be
programmed to at least the reset value always. The
corresponding source code updates are added in this change.

Change-Id: I1da1120b5c5a3dda7f7122eacac9e68bfede88e4
Signed-off-by: default avatarVenkat Chinta <vchinta@codeaurora.org>
parent edcd9db1

drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c

+10 −8
Original line number Diff line number Diff line
@@ -4529,16 +4529,16 @@ static int cam_ife_hw_mgr_handle_reg_update_in_bus( 


		hw_res_left = isp_ife_out_res->hw_res[0];

		if (hw_res_left && (evt_payload->core_index ==

			hw_res_left->hw_intf->hw_idx))

			hw_res_left->hw_intf->hw_idx)) {

			rup_status = hw_res_left->bottom_half_handler(

				hw_res_left, evt_payload);

	}



	CAM_DBG(CAM_ISP, "Exit rup_status = %d", rup_status);

			if (rup_status == 0)

				break;

		}

	}



	if (!rup_status) {

		CAM_DBG(CAM_ISP, "Exit rup_status = %d", rup_status);



		if (!atomic_read(&ife_hwr_mgr_ctx->overflow_pending))

			ife_hwr_irq_rup_cb(

				ife_hwr_mgr_ctx->common.cb_priv,
@@ -4546,6 +4546,8 @@ static int cam_ife_hw_mgr_handle_reg_update_in_bus( 
				&rup_event_data);

	}



	CAM_DBG(CAM_ISP, "Exit rup_status = %d", rup_status);



	return 0;

}

drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_ver3.c

+15 −8
Original line number Diff line number Diff line
@@ -968,7 +968,7 @@ static int cam_vfe_bus_ver3_acquire_wm( 
			rsrc_data->height = 0;

			rsrc_data->stride = CAM_VFE_RDI_BUS_DEFAULT_STRIDE;

			rsrc_data->pack_fmt = 0x0;

			rsrc_data->en_cfg = 0x3;

			rsrc_data->en_cfg = (0x1 << 16) | 0x1;

			break;

		case CAM_FORMAT_PLAIN8:

			rsrc_data->en_cfg = 0x1;
@@ -985,7 +985,7 @@ static int cam_vfe_bus_ver3_acquire_wm( 
			rsrc_data->height = 0;

			rsrc_data->stride = CAM_VFE_RDI_BUS_DEFAULT_STRIDE;

			rsrc_data->pack_fmt = 0x0;

			rsrc_data->en_cfg = 0x3;

			rsrc_data->en_cfg = (0x1 << 16) | 0x1;

			break;

		case CAM_FORMAT_PLAIN64:

			rsrc_data->en_cfg = 0x1;
@@ -1083,18 +1083,24 @@ static int cam_vfe_bus_ver3_acquire_wm( 
			return -EINVAL;

		}

		rsrc_data->en_cfg = 0x1;

	} else if (rsrc_data->index > 11 && rsrc_data->index < 21) {

		/* WM 12-20 stats */

	} else if (rsrc_data->index == 20) {

		/* WM 20 stats BAF */

		rsrc_data->width = 0;

		rsrc_data->height = 0;

		rsrc_data->stride = 1;

		rsrc_data->en_cfg = 0x3;

		rsrc_data->en_cfg = (0x2 << 16) | 0x1;

	} else if (rsrc_data->index > 11 && rsrc_data->index < 20) {

		/* WM 12-19 stats */

		rsrc_data->width = 0;

		rsrc_data->height = 0;

		rsrc_data->stride = 1;

		rsrc_data->en_cfg = (0x1 << 16) | 0x1;

	} else if (rsrc_data->index == 11 || rsrc_data->index == 21) {

		/* WM 21/11 PDAF/2PD */

		rsrc_data->width = 0;

		rsrc_data->height = 0;

		rsrc_data->stride = 1;

		rsrc_data->en_cfg = 0x3;

		rsrc_data->en_cfg = (0x1 << 16) | 0x1;

		if (vfe_out_res_id == CAM_VFE_BUS_VER3_VFE_OUT_PDAF)

			/* LSB aligned */

			rsrc_data->pack_fmt |= 0x10;
@@ -1111,7 +1117,7 @@ static int cam_vfe_bus_ver3_acquire_wm( 
			rsrc_data->width = 0;

			rsrc_data->height = 0;

			rsrc_data->stride = 1;

			rsrc_data->en_cfg = 0x3;

			rsrc_data->en_cfg = (0x1 << 16) | 0x1;

			/* LSB aligned */

			rsrc_data->pack_fmt |= 0x10;

			break;
@@ -2885,7 +2891,8 @@ static int cam_vfe_bus_ver3_init_hw(void *hw_priv, 
	}



	// no clock gating at bus input

	cam_io_w_mb(0xFFFFF, bus_priv->common_data.mem_base +

	CAM_INFO(CAM_ISP, "Overriding clock gating at bus input");

	cam_io_w_mb(0x3FFFFFF, bus_priv->common_data.mem_base +

		bus_priv->common_data.common_reg->cgc_ovd);



	// BUS_WR_TEST_BUS_CTRL

drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_ver3.c

+8 −3
Original line number Diff line number Diff line
@@ -18,6 +18,7 @@ 
#include "cam_cpas_api.h"



#define CAM_VFE_CAMIF_IRQ_SOF_DEBUG_CNT_MAX 2

#define CAM_VFE_CAMIF_VER3_CORE_CFG_0_DEFAULT 0x2800



struct cam_vfe_mux_camif_ver3_data {

	void __iomem                                *mem_base;
@@ -256,7 +257,11 @@ static int cam_vfe_camif_ver3_resource_start( 
	cam_io_w_mb(val,

		rsrc_data->mem_base + rsrc_data->camif_reg->module_cfg);

	CAM_DBG(CAM_ISP, "write module_cfg val = 0x%x", val);

	val = 0x0;



	val = cam_io_r_mb(rsrc_data->mem_base +

		rsrc_data->camif_reg->module_cfg);



	val |= CAM_VFE_CAMIF_VER3_CORE_CFG_0_DEFAULT;



	/* AF stitching by hw disabled by default

	 * PP CAMIF currently operates only in offline mode
@@ -274,8 +279,8 @@ static int cam_vfe_camif_ver3_resource_start( 
	if (rsrc_data->sync_mode == CAM_ISP_HW_SYNC_SLAVE)

		val |= (1 << rsrc_data->reg_data->pp_extern_reg_update_shift);



	cam_io_w_mb(val,

		rsrc_data->mem_base + rsrc_data->common_reg->core_cfg_0);

	cam_io_w_mb(val, rsrc_data->mem_base +

		rsrc_data->common_reg->core_cfg_0);



	/* epoch config */

	switch (soc_private->cpas_version) {