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Commit 4a1caed3 authored by Uwe Kleine-König's avatar Uwe Kleine-König Committed by Stephen Boyd
Browse files

clk: make several parent names const 



Since commit 2893c379 ("clk: make strings in parent name arrays
const") the name of parent clocks can be const. So add more const in
several clock drivers.

Signed-off-by: default avatarUwe Kleine-König <u.kleine-koenig@pengutronix.de>
Acked-by: default avatarHeiko Stuebner <heiko@sntech.de>
Acked-by: default avatarSylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
parent 90acb40f

drivers/clk/hisilicon/clk-hi3620.c

+35 −35
Original line number Diff line number Diff line
@@ -38,44 +38,44 @@ 
#include "clk.h"



/* clock parent list */

static const char *timer0_mux_p[] __initdata = { "osc32k", "timerclk01", };

static const char *timer1_mux_p[] __initdata = { "osc32k", "timerclk01", };

static const char *timer2_mux_p[] __initdata = { "osc32k", "timerclk23", };

static const char *timer3_mux_p[] __initdata = { "osc32k", "timerclk23", };

static const char *timer4_mux_p[] __initdata = { "osc32k", "timerclk45", };

static const char *timer5_mux_p[] __initdata = { "osc32k", "timerclk45", };

static const char *timer6_mux_p[] __initdata = { "osc32k", "timerclk67", };

static const char *timer7_mux_p[] __initdata = { "osc32k", "timerclk67", };

static const char *timer8_mux_p[] __initdata = { "osc32k", "timerclk89", };

static const char *timer9_mux_p[] __initdata = { "osc32k", "timerclk89", };

static const char *uart0_mux_p[] __initdata = { "osc26m", "pclk", };

static const char *uart1_mux_p[] __initdata = { "osc26m", "pclk", };

static const char *uart2_mux_p[] __initdata = { "osc26m", "pclk", };

static const char *uart3_mux_p[] __initdata = { "osc26m", "pclk", };

static const char *uart4_mux_p[] __initdata = { "osc26m", "pclk", };

static const char *spi0_mux_p[] __initdata = { "osc26m", "rclk_cfgaxi", };

static const char *spi1_mux_p[] __initdata = { "osc26m", "rclk_cfgaxi", };

static const char *spi2_mux_p[] __initdata = { "osc26m", "rclk_cfgaxi", };

static const char *const timer0_mux_p[] __initconst = { "osc32k", "timerclk01", };

static const char *const timer1_mux_p[] __initconst = { "osc32k", "timerclk01", };

static const char *const timer2_mux_p[] __initconst = { "osc32k", "timerclk23", };

static const char *const timer3_mux_p[] __initconst = { "osc32k", "timerclk23", };

static const char *const timer4_mux_p[] __initconst = { "osc32k", "timerclk45", };

static const char *const timer5_mux_p[] __initconst = { "osc32k", "timerclk45", };

static const char *const timer6_mux_p[] __initconst = { "osc32k", "timerclk67", };

static const char *const timer7_mux_p[] __initconst = { "osc32k", "timerclk67", };

static const char *const timer8_mux_p[] __initconst = { "osc32k", "timerclk89", };

static const char *const timer9_mux_p[] __initconst = { "osc32k", "timerclk89", };

static const char *const uart0_mux_p[] __initconst = { "osc26m", "pclk", };

static const char *const uart1_mux_p[] __initconst = { "osc26m", "pclk", };

static const char *const uart2_mux_p[] __initconst = { "osc26m", "pclk", };

static const char *const uart3_mux_p[] __initconst = { "osc26m", "pclk", };

static const char *const uart4_mux_p[] __initconst = { "osc26m", "pclk", };

static const char *const spi0_mux_p[] __initconst = { "osc26m", "rclk_cfgaxi", };

static const char *const spi1_mux_p[] __initconst = { "osc26m", "rclk_cfgaxi", };

static const char *const spi2_mux_p[] __initconst = { "osc26m", "rclk_cfgaxi", };

/* share axi parent */

static const char *saxi_mux_p[] __initdata = { "armpll3", "armpll2", };

static const char *pwm0_mux_p[] __initdata = { "osc32k", "osc26m", };

static const char *pwm1_mux_p[] __initdata = { "osc32k", "osc26m", };

static const char *sd_mux_p[] __initdata = { "armpll2", "armpll3", };

static const char *mmc1_mux_p[] __initdata = { "armpll2", "armpll3", };

static const char *mmc1_mux2_p[] __initdata = { "osc26m", "mmc1_div", };

static const char *g2d_mux_p[] __initdata = { "armpll2", "armpll3", };

static const char *venc_mux_p[] __initdata = { "armpll2", "armpll3", };

static const char *vdec_mux_p[] __initdata = { "armpll2", "armpll3", };

static const char *vpp_mux_p[] __initdata = { "armpll2", "armpll3", };

static const char *edc0_mux_p[] __initdata = { "armpll2", "armpll3", };

static const char *ldi0_mux_p[] __initdata = { "armpll2", "armpll4",

static const char *const saxi_mux_p[] __initconst = { "armpll3", "armpll2", };

static const char *const pwm0_mux_p[] __initconst = { "osc32k", "osc26m", };

static const char *const pwm1_mux_p[] __initconst = { "osc32k", "osc26m", };

static const char *const sd_mux_p[] __initconst = { "armpll2", "armpll3", };

static const char *const mmc1_mux_p[] __initconst = { "armpll2", "armpll3", };

static const char *const mmc1_mux2_p[] __initconst = { "osc26m", "mmc1_div", };

static const char *const g2d_mux_p[] __initconst = { "armpll2", "armpll3", };

static const char *const venc_mux_p[] __initconst = { "armpll2", "armpll3", };

static const char *const vdec_mux_p[] __initconst = { "armpll2", "armpll3", };

static const char *const vpp_mux_p[] __initconst = { "armpll2", "armpll3", };

static const char *const edc0_mux_p[] __initconst = { "armpll2", "armpll3", };

static const char *const ldi0_mux_p[] __initconst = { "armpll2", "armpll4",

					     "armpll3", "armpll5", };

static const char *edc1_mux_p[] __initdata = { "armpll2", "armpll3", };

static const char *ldi1_mux_p[] __initdata = { "armpll2", "armpll4",

static const char *const edc1_mux_p[] __initconst = { "armpll2", "armpll3", };

static const char *const ldi1_mux_p[] __initconst = { "armpll2", "armpll4",

					     "armpll3", "armpll5", };

static const char *rclk_hsic_p[] __initdata = { "armpll3", "armpll2", };

static const char *mmc2_mux_p[] __initdata = { "armpll2", "armpll3", };

static const char *mmc3_mux_p[] __initdata = { "armpll2", "armpll3", };

static const char *const rclk_hsic_p[] __initconst = { "armpll3", "armpll2", };

static const char *const mmc2_mux_p[] __initconst = { "armpll2", "armpll3", };

static const char *const mmc3_mux_p[] __initconst = { "armpll2", "armpll3", };





/* fixed rate clocks */

drivers/clk/hisilicon/clk-hix5hd2.c

+3 −3
Original line number Diff line number Diff line
@@ -46,15 +46,15 @@ static struct hisi_fixed_rate_clock hix5hd2_fixed_rate_clks[] __initdata = { 
	{ HIX5HD2_FIXED_83M, "83m", NULL, CLK_IS_ROOT, 83333333, },

};



static const char *sfc_mux_p[] __initdata = {

static const char *const sfc_mux_p[] __initconst = {

		"24m", "150m", "200m", "100m", "75m", };

static u32 sfc_mux_table[] = {0, 4, 5, 6, 7};



static const char *sdio_mux_p[] __initdata = {

static const char *const sdio_mux_p[] __initconst = {

		"75m", "100m", "50m", "15m", };

static u32 sdio_mux_table[] = {0, 1, 2, 3};



static const char *fephy_mux_p[] __initdata = { "25m", "125m"};

static const char *const fephy_mux_p[] __initconst = { "25m", "125m"};

static u32 fephy_mux_table[] = {0, 1};

drivers/clk/hisilicon/clk.h

+1 −1
Original line number Diff line number Diff line
@@ -55,7 +55,7 @@ struct hisi_fixed_factor_clock { 
struct hisi_mux_clock {

	unsigned int		id;

	const char		*name;

	const char		**parent_names;

	const char		*const *parent_names;

	u8			num_parents;

	unsigned long		flags;

	unsigned long		offset;

drivers/clk/mxs/clk-imx23.c

+6 −6
Original line number Diff line number Diff line
@@ -77,12 +77,12 @@ static void __init clk_misc_init(void) 
	writel_relaxed(30 << BP_FRAC_IOFRAC, FRAC + SET);

}



static const char *sel_pll[]  __initdata = { "pll", "ref_xtal", };

static const char *sel_cpu[]  __initdata = { "ref_cpu", "ref_xtal", };

static const char *sel_pix[]  __initdata = { "ref_pix", "ref_xtal", };

static const char *sel_io[]   __initdata = { "ref_io", "ref_xtal", };

static const char *cpu_sels[] __initdata = { "cpu_pll", "cpu_xtal", };

static const char *emi_sels[] __initdata = { "emi_pll", "emi_xtal", };

static const char *const sel_pll[]  __initconst = { "pll", "ref_xtal", };

static const char *const sel_cpu[]  __initconst = { "ref_cpu", "ref_xtal", };

static const char *const sel_pix[]  __initconst = { "ref_pix", "ref_xtal", };

static const char *const sel_io[]   __initconst = { "ref_io", "ref_xtal", };

static const char *const cpu_sels[] __initconst = { "cpu_pll", "cpu_xtal", };

static const char *const emi_sels[] __initconst = { "emi_pll", "emi_xtal", };



enum imx23_clk {

	ref_xtal, pll, ref_cpu, ref_emi, ref_pix, ref_io, saif_sel,

drivers/clk/mxs/clk-imx28.c

+9 −9
Original line number Diff line number Diff line
@@ -125,15 +125,15 @@ static void __init clk_misc_init(void) 
	writel_relaxed(val, FRAC0);

}



static const char *sel_cpu[]  __initdata = { "ref_cpu", "ref_xtal", };

static const char *sel_io0[]  __initdata = { "ref_io0", "ref_xtal", };

static const char *sel_io1[]  __initdata = { "ref_io1", "ref_xtal", };

static const char *sel_pix[]  __initdata = { "ref_pix", "ref_xtal", };

static const char *sel_gpmi[] __initdata = { "ref_gpmi", "ref_xtal", };

static const char *sel_pll0[] __initdata = { "pll0", "ref_xtal", };

static const char *cpu_sels[] __initdata = { "cpu_pll", "cpu_xtal", };

static const char *emi_sels[] __initdata = { "emi_pll", "emi_xtal", };

static const char *ptp_sels[] __initdata = { "ref_xtal", "pll0", };

static const char *const sel_cpu[]  __initconst = { "ref_cpu", "ref_xtal", };

static const char *const sel_io0[]  __initconst = { "ref_io0", "ref_xtal", };

static const char *const sel_io1[]  __initconst = { "ref_io1", "ref_xtal", };

static const char *const sel_pix[]  __initconst = { "ref_pix", "ref_xtal", };

static const char *const sel_gpmi[] __initconst = { "ref_gpmi", "ref_xtal", };

static const char *const sel_pll0[] __initconst = { "pll0", "ref_xtal", };

static const char *const cpu_sels[] __initconst = { "cpu_pll", "cpu_xtal", };

static const char *const emi_sels[] __initconst = { "emi_pll", "emi_xtal", };

static const char *const ptp_sels[] __initconst = { "ref_xtal", "pll0", };



enum imx28_clk {

	ref_xtal, pll0, pll1, pll2, ref_cpu, ref_emi, ref_io0, ref_io1,