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Commit 4a0156fb authored by Steven J. Hill's avatar Steven J. Hill Committed by Ralf Baechle
Browse files

MIPS: features: Add initial support for Segmentation Control registers 



MIPS32R3 introduced a new set of Segmentation Control registers which
increase the flexibility of the segmented-based memory scheme.

Signed-off-by: default avatarSteven J. Hill <Steven.Hill@imgtec.com>
Signed-off-by: default avatarMarkos Chandras <markos.chandras@imgtec.com>
Signed-off-by: default avatarJohn Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6131/
parent 1745c1ef

arch/mips/include/asm/cpu-features.h

+4 −0
Original line number Diff line number Diff line
@@ -23,6 +23,10 @@ 
#ifndef cpu_has_tlbinv

#define cpu_has_tlbinv		(cpu_data[0].options & MIPS_CPU_TLBINV)

#endif

#ifndef cpu_has_segments

#define cpu_has_segments	(cpu_data[0].options & MIPS_CPU_SEGMENTS)

#endif





/*

 * For the moment we don't consider R6000 and R8000 so we can assume that

arch/mips/include/asm/cpu.h

+1 −0
Original line number Diff line number Diff line
@@ -352,6 +352,7 @@ enum cpu_type_enum { 
#define MIPS_CPU_RIXI		0x00800000 /* CPU has TLB Read/eXec Inhibit */

#define MIPS_CPU_MICROMIPS	0x01000000 /* CPU has microMIPS capability */

#define MIPS_CPU_TLBINV		0x02000000 /* CPU supports TLBINV/F */

#define MIPS_CPU_SEGMENTS	0x04000000 /* CPU supports Segmentation Control registers */



/*

 * CPU ASE encodings

arch/mips/include/asm/mipsregs.h

+29 −0
Original line number Diff line number Diff line
@@ -664,6 +664,26 @@ 
#define MIPS_FPIR_L		(_ULCAST_(1) << 21)

#define MIPS_FPIR_F64		(_ULCAST_(1) << 22)



/*

 * Bits in the MIPS32 Memory Segmentation registers.

 */

#define MIPS_SEGCFG_PA_SHIFT	9

#define MIPS_SEGCFG_PA		(_ULCAST_(127) << MIPS_SEGCFG_PA_SHIFT)

#define MIPS_SEGCFG_AM_SHIFT	4

#define MIPS_SEGCFG_AM		(_ULCAST_(7) << MIPS_SEGCFG_AM_SHIFT)

#define MIPS_SEGCFG_EU_SHIFT	3

#define MIPS_SEGCFG_EU		(_ULCAST_(1) << MIPS_SEGCFG_EU_SHIFT)

#define MIPS_SEGCFG_C_SHIFT	0

#define MIPS_SEGCFG_C		(_ULCAST_(7) << MIPS_SEGCFG_C_SHIFT)



#define MIPS_SEGCFG_UUSK	_ULCAST_(7)

#define MIPS_SEGCFG_USK		_ULCAST_(5)

#define MIPS_SEGCFG_MUSUK	_ULCAST_(4)

#define MIPS_SEGCFG_MUSK	_ULCAST_(3)

#define MIPS_SEGCFG_MSK		_ULCAST_(2)

#define MIPS_SEGCFG_MK		_ULCAST_(1)

#define MIPS_SEGCFG_UK		_ULCAST_(0)



#ifndef __ASSEMBLY__



/*
@@ -1138,6 +1158,15 @@ do { \ 
#define read_c0_ebase()		__read_32bit_c0_register($15, 1)

#define write_c0_ebase(val)	__write_32bit_c0_register($15, 1, val)



/* MIPSR3 */

#define read_c0_segctl0()	__read_32bit_c0_register($5, 2)

#define write_c0_segctl0(val)	__write_32bit_c0_register($5, 2, val)



#define read_c0_segctl1()	__read_32bit_c0_register($5, 3)

#define write_c0_segctl1(val)	__write_32bit_c0_register($5, 3, val)



#define read_c0_segctl2()	__read_32bit_c0_register($5, 4)

#define write_c0_segctl2(val)	__write_32bit_c0_register($5, 4, val)



/* Cavium OCTEON (cnMIPS) */

#define read_c0_cvmcount()	__read_ulong_c0_register($9, 6)

arch/mips/kernel/cpu-probe.c

+2 −0
Original line number Diff line number Diff line
@@ -272,6 +272,8 @@ static inline unsigned int decode_config3(struct cpuinfo_mips *c) 
		c->options |= MIPS_CPU_MICROMIPS;

	if (config3 & MIPS_CONF3_VZ)

		c->ases |= MIPS_ASE_VZ;

	if (config3 & MIPS_CONF3_SC)

		c->options |= MIPS_CPU_SEGMENTS;



	return config3 & MIPS_CONF_M;

}