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Commit 49f91ac3 authored by Derek Basehore's avatar Derek Basehore Committed by Lee Jones
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mfd: cros ec: spi: Increase EC transaction delay 



50 us is not a long enough delay between EC transactions. At least 70 us
are needed for the 16 MHz STM32L part. Increase the delay to 200 us for
an extra safety margin.

Reviewed-by: default avatarRandall Spangler <rspangler@chromium.org>
Signed-off-by: default avatarDerek Basehore <dbasehore@chromium.org>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
Signed-off-by: default avatarLee Jones <lee.jones@linaro.org>
parent 9981a314

drivers/mfd/cros_ec_spi.c

+4 −3
Original line number Diff line number Diff line
@@ -50,10 +50,11 @@ 
/*

  * Time between raising the SPI chip select (for the end of a

  * transaction) and dropping it again (for the next transaction).

  * If we go too fast, the EC will miss the transaction. It seems

  * that 50us is enough with the 16MHz STM32 EC.

  * If we go too fast, the EC will miss the transaction. We know that we

  * need at least 70 us with the 16 MHz STM32 EC, so go with 200 us to be

  * safe.

  */

#define EC_SPI_RECOVERY_TIME_NS	(50 * 1000)

#define EC_SPI_RECOVERY_TIME_NS	(200 * 1000)



/**

 * struct cros_ec_spi - information about a SPI-connected EC