Unverified Commit 49530e64 authored Apr 17, 2018 by sxauwsk Committed by Mark Brown Apr 18, 2018

spi: cadence: Add usleep_range() for cdns_spi_fill_tx_fifo()



In case of xspi work in busy condition, may send bytes failed.
once something wrong, spi controller did't work any more

My test found this situation appear in both of read/write process.
so when TX FIFO is full, add one byte delay before send data;

Signed-off-by: sxauwsk <sxauwsk@163.com>
Signed-off-by: Mark Brown <broonie@kernel.org>

parent 10b46408

drivers/spi/spi-cadence.c

+8 −0

Original line number	Diff line number	Diff line
		@@ -313,6 +313,14 @@ static void cdns_spi_fill_tx_fifo(struct cdns_spi *xspi)

		while ((trans_cnt < CDNS_SPI_FIFO_DEPTH) &&
		(xspi->tx_bytes > 0)) {

		/* When xspi in busy condition, bytes may send failed,
		* then spi control did't work thoroughly, add one byte delay
		*/
		if (cdns_spi_read(xspi, CDNS_SPI_ISR) &
		CDNS_SPI_IXR_TXFULL)
		usleep_range(10, 20);

		if (xspi->txbuf)
		cdns_spi_write(xspi, CDNS_SPI_TXD, *xspi->txbuf++);
		else