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Commit 4945c1d6 authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'r8169-next' 



Chunhao Lin says:

====================
r8169:change hardware setting

This patch series contains two hardware setting modification to prevent
hardware become abnormal.
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 66813d4d 003609da

drivers/net/ethernet/realtek/r8169.c

+22 −11
Original line number Diff line number Diff line
@@ -1377,6 +1377,16 @@ DECLARE_RTL_COND(rtl_ocp_tx_cond) 
	return RTL_R8(IBISR0) & 0x02;

}



static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)

{

	void __iomem *ioaddr = tp->mmio_addr;



	RTL_W8(IBCR2, RTL_R8(IBCR2) & ~0x01);

	rtl_msleep_loop_wait_low(tp, &rtl_ocp_tx_cond, 50, 2000);

	RTL_W8(IBISR0, RTL_R8(IBISR0) | 0x20);

	RTL_W8(IBCR0, RTL_R8(IBCR0) & ~0x01);

}



static void rtl8168dp_driver_start(struct rtl8169_private *tp)

{

	rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
@@ -1417,12 +1427,7 @@ static void rtl8168dp_driver_stop(struct rtl8169_private *tp) 


static void rtl8168ep_driver_stop(struct rtl8169_private *tp)

{

	void __iomem *ioaddr = tp->mmio_addr;



	RTL_W8(IBCR2, RTL_R8(IBCR2) & ~0x01);

	rtl_msleep_loop_wait_low(tp, &rtl_ocp_tx_cond, 50, 2000);

	RTL_W8(IBISR0, RTL_R8(IBISR0) | 0x20);

	RTL_W8(IBCR0, RTL_R8(IBCR0) & ~0x01);

	rtl8168ep_stop_cmac(tp);

	ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);

	ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);

	rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10);
@@ -5934,7 +5939,6 @@ static void rtl_hw_start_8168g_1(struct rtl8169_private *tp) 
	rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);

	rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f, ERIAR_EXGMAC);



	RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);

	RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);

	RTL_W8(MaxTxPacketSize, EarlySize);
@@ -6027,7 +6031,6 @@ static void rtl_hw_start_8168h_1(struct rtl8169_private *tp) 


	rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);



	RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);

	RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);

	RTL_W8(MaxTxPacketSize, EarlySize);
@@ -6091,6 +6094,8 @@ static void rtl_hw_start_8168ep(struct rtl8169_private *tp) 
	void __iomem *ioaddr = tp->mmio_addr;

	struct pci_dev *pdev = tp->pci_dev;



	rtl8168ep_stop_cmac(tp);



	RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);



	rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
@@ -6109,7 +6114,6 @@ static void rtl_hw_start_8168ep(struct rtl8169_private *tp) 


	rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);



	RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);

	RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);

	RTL_W8(MaxTxPacketSize, EarlySize);
@@ -8005,6 +8009,12 @@ static void rtl_hw_init_8168g(struct rtl8169_private *tp) 
		return;

}



static void rtl_hw_init_8168ep(struct rtl8169_private *tp)

{

	rtl8168ep_stop_cmac(tp);

	rtl_hw_init_8168g(tp);

}



static void rtl_hw_initialize(struct rtl8169_private *tp)

{

	switch (tp->mac_version) {
@@ -8017,12 +8027,13 @@ static void rtl_hw_initialize(struct rtl8169_private *tp) 
	case RTL_GIGA_MAC_VER_46:

	case RTL_GIGA_MAC_VER_47:

	case RTL_GIGA_MAC_VER_48:

		rtl_hw_init_8168g(tp);

		break;

	case RTL_GIGA_MAC_VER_49:

	case RTL_GIGA_MAC_VER_50:

	case RTL_GIGA_MAC_VER_51:

		rtl_hw_init_8168g(tp);

		rtl_hw_init_8168ep(tp);

		break;



	default:

		break;

	}