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Commit 488a96e5 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "spi: spi-geni-qcom: Don't initialize GSI channels for FIFO/SE_DMA mode"

parents ae836848 d4f73714

drivers/spi/spi-geni-qcom.c

+62 −54
Original line number Diff line number Diff line
@@ -805,13 +805,62 @@ static int spi_geni_unprepare_message(struct spi_master *spi_mas, 
	return 0;

}



static void spi_geni_set_sampling_rate(struct spi_geni_master *mas,

	unsigned int major, unsigned int minor)

{

	u32 cpol, cpha, cfg_reg108, cfg_reg109, cfg_seq_start;



	cpol = geni_read_reg(mas->base, SE_SPI_CPOL);

	cpha = geni_read_reg(mas->base, SE_SPI_CPHA);

	cfg_reg108 = geni_read_reg(mas->base, SE_GENI_CFG_REG108);

	cfg_reg109 = geni_read_reg(mas->base, SE_GENI_CFG_REG109);

	/* clear CPOL bit */

	cfg_reg108 &= ~(1 << CPOL_CTRL_SHFT);



	if (major == 1 && minor == 0) {

		/* Write 1 to RX_SI_EN2IO_DELAY reg */

		cfg_reg108 &= ~(0x7 << RX_SI_EN2IO_DELAY_SHFT);

		cfg_reg108 |= (1 << RX_SI_EN2IO_DELAY_SHFT);

		/* Write 0 to RX_IO_POS_FF_EN_SEL reg */

		cfg_reg108 &= ~(1 << RX_IO_POS_FF_EN_SEL_SHFT);

	} else if ((major < 2) || (major == 2 && minor < 5)) {

		/* Write 0 to RX_IO_EN2CORE_EN_DELAY reg */

		cfg_reg108 &= ~(0x7 << RX_IO_EN2CORE_EN_DELAY_SHFT);

	} else {

		/*

		 * Write miso_sampling_ctrl_set to

		 * RX_IO_EN2CORE_EN_DELAY reg

		 */

		cfg_reg108 &= ~(0x7 << RX_IO_EN2CORE_EN_DELAY_SHFT);

		cfg_reg108 |= (mas->miso_sampling_ctrl_val <<

				RX_IO_EN2CORE_EN_DELAY_SHFT);

	}



	geni_write_reg(cfg_reg108, mas->base, SE_GENI_CFG_REG108);



	if (cpol == 0 && cpha == 0)

		cfg_reg109 = 1;

	else if (cpol == 1 && cpha == 0)

		cfg_reg109 = 0;

	geni_write_reg(cfg_reg109, mas->base,

				SE_GENI_CFG_REG109);

	if (!(major == 1 && minor == 0))

		geni_write_reg(1, mas->base, SE_GENI_CFG_SEQ_START);

	cfg_reg108 = geni_read_reg(mas->base, SE_GENI_CFG_REG108);

	cfg_reg109 = geni_read_reg(mas->base, SE_GENI_CFG_REG109);

	cfg_seq_start = geni_read_reg(mas->base, SE_GENI_CFG_SEQ_START);



	GENI_SE_DBG(mas->ipc, false, mas->dev,

		"%s cfg108: 0x%x cfg109: 0x%x cfg_seq_start: 0x%x\n",

		__func__, cfg_reg108, cfg_reg109, cfg_seq_start);

}



static int spi_geni_prepare_transfer_hardware(struct spi_master *spi)

{

	struct spi_geni_master *mas = spi_master_get_devdata(spi);

	int ret = 0, count = 0;

	u32 max_speed = spi->cur_msg->spi->max_speed_hz;

	struct se_geni_rsc *rsc = &mas->spi_rsc;

	u32 cpol, cpha, cfg_reg108, cfg_reg109, cfg_seq_start;



	/* Adjust the IB based on the max speed of the slave.*/

	rsc->ib = max_speed * DEFAULT_BUS_WIDTH;
@@ -864,11 +913,17 @@ static int spi_geni_prepare_transfer_hardware(struct spi_master *spi) 
		/* Transmit an entire FIFO worth of data per IRQ */

		mas->tx_wm = 1;



		mas->shared_se =

			(geni_read_reg(mas->base, GENI_IF_FIFO_DISABLE_RO) &

							FIFO_IF_DISABLE);

		if (mas->shared_se) {

			mas->tx = dma_request_slave_channel(mas->dev, "tx");

			if (IS_ERR_OR_NULL(mas->tx)) {

			dev_info(mas->dev, "Failed to get tx DMA ch %ld\n",

				dev_info(mas->dev,

					"Failed to get tx DMA ch %ld\n",

							PTR_ERR(mas->tx));

		} else {

				goto setup_ipc;

			}

			mas->rx = dma_request_slave_channel(mas->dev, "rx");

			if (IS_ERR_OR_NULL(mas->rx)) {

				dev_info(mas->dev, "Failed to get rx DMA ch %ld\n",
@@ -933,56 +988,9 @@ static int spi_geni_prepare_transfer_hardware(struct spi_master *spi) 
			__func__, major, minor, step, mas->oversampling);

		}



		if (!mas->set_miso_sampling)

			goto shared_se;

		if (mas->set_miso_sampling)

			spi_geni_set_sampling_rate(mas, major, minor);



		cpol = geni_read_reg(mas->base, SE_SPI_CPOL);

		cpha = geni_read_reg(mas->base, SE_SPI_CPHA);

		cfg_reg108 = geni_read_reg(mas->base, SE_GENI_CFG_REG108);

		cfg_reg109 = geni_read_reg(mas->base, SE_GENI_CFG_REG109);

		/* clear CPOL bit */

		cfg_reg108 &= ~(1 << CPOL_CTRL_SHFT);



		if (major == 1 && minor == 0) {

			/* Write 1 to RX_SI_EN2IO_DELAY reg */

			cfg_reg108 &= ~(0x7 << RX_SI_EN2IO_DELAY_SHFT);

			cfg_reg108 |= (1 << RX_SI_EN2IO_DELAY_SHFT);

			/* Write 0 to RX_IO_POS_FF_EN_SEL reg */

			cfg_reg108 &= ~(1 << RX_IO_POS_FF_EN_SEL_SHFT);

		} else if ((major < 2) || (major == 2 && minor < 5)) {

			/* Write 0 to RX_IO_EN2CORE_EN_DELAY reg */

			cfg_reg108 &= ~(0x7 << RX_IO_EN2CORE_EN_DELAY_SHFT);

		} else {

			/*

			 * Write miso_sampling_ctrl_set to

			 * RX_IO_EN2CORE_EN_DELAY reg

			 */

			cfg_reg108 &= ~(0x7 << RX_IO_EN2CORE_EN_DELAY_SHFT);

			cfg_reg108 |= (mas->miso_sampling_ctrl_val <<

					RX_IO_EN2CORE_EN_DELAY_SHFT);

		}



		geni_write_reg(cfg_reg108, mas->base, SE_GENI_CFG_REG108);



		if (cpol == 0 && cpha == 0)

			cfg_reg109 = 1;

		else if (cpol == 1 && cpha == 0)

			cfg_reg109 = 0;

		geni_write_reg(cfg_reg109, mas->base,

					SE_GENI_CFG_REG109);

		if (!(major == 1 && minor == 0))

			geni_write_reg(1, mas->base, SE_GENI_CFG_SEQ_START);

		cfg_reg108 = geni_read_reg(mas->base, SE_GENI_CFG_REG108);

		cfg_reg109 = geni_read_reg(mas->base, SE_GENI_CFG_REG109);

		cfg_seq_start = geni_read_reg(mas->base, SE_GENI_CFG_SEQ_START);



		GENI_SE_DBG(mas->ipc, false, mas->dev,

			"%s cfg108: 0x%x cfg109: 0x%x cfg_seq_start: 0x%x\n",

			__func__, cfg_reg108, cfg_reg109, cfg_seq_start);

shared_se:

		mas->shared_se =

			(geni_read_reg(mas->base, GENI_IF_FIFO_DISABLE_RO) &

							FIFO_IF_DISABLE);

		if (mas->dis_autosuspend)

			GENI_SE_DBG(mas->ipc, false, mas->dev,

					"Auto Suspend is disabled\n");