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Commit 4853bbb6 authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/amdgpu/gfx: move mec parameter setup into sw_init 



This will allow us to share more mec code.

Reviewed-by: default avatarAlex Xie <AlexBin.Xie@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 71c37505

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

+15 −15
Original line number Diff line number Diff line
@@ -2817,21 +2817,6 @@ static int gfx_v7_0_mec_init(struct amdgpu_device *adev) 


	bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);



	switch (adev->asic_type) {

	case CHIP_KAVERI:

		adev->gfx.mec.num_mec = 2;

		break;

	case CHIP_BONAIRE:

	case CHIP_HAWAII:

	case CHIP_KABINI:

	case CHIP_MULLINS:

	default:

		adev->gfx.mec.num_mec = 1;

		break;

	}

	adev->gfx.mec.num_pipe_per_mec = 4;

	adev->gfx.mec.num_queue_per_pipe = 8;



	/* take ownership of the relevant compute queues */

	amdgpu_gfx_compute_queue_acquire(adev);
@@ -4723,6 +4708,21 @@ static int gfx_v7_0_sw_init(void *handle) 
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	int i, j, k, r, ring_id;



	switch (adev->asic_type) {

	case CHIP_KAVERI:

		adev->gfx.mec.num_mec = 2;

		break;

	case CHIP_BONAIRE:

	case CHIP_HAWAII:

	case CHIP_KABINI:

	case CHIP_MULLINS:

	default:

		adev->gfx.mec.num_mec = 1;

		break;

	}

	adev->gfx.mec.num_pipe_per_mec = 4;

	adev->gfx.mec.num_queue_per_pipe = 8;



	/* EOP Event */

	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 181, &adev->gfx.eop_irq);

	if (r)

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

+19 −19
Original line number Diff line number Diff line
@@ -1387,25 +1387,6 @@ static int gfx_v8_0_mec_init(struct amdgpu_device *adev) 


	bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);



	switch (adev->asic_type) {

	case CHIP_FIJI:

	case CHIP_TONGA:

	case CHIP_POLARIS11:

	case CHIP_POLARIS12:

	case CHIP_POLARIS10:

	case CHIP_CARRIZO:

		adev->gfx.mec.num_mec = 2;

		break;

	case CHIP_TOPAZ:

	case CHIP_STONEY:

	default:

		adev->gfx.mec.num_mec = 1;

		break;

	}



	adev->gfx.mec.num_pipe_per_mec = 4;

	adev->gfx.mec.num_queue_per_pipe = 8;



	/* take ownership of the relevant compute queues */

	amdgpu_gfx_compute_queue_acquire(adev);
@@ -2009,6 +1990,25 @@ static int gfx_v8_0_sw_init(void *handle) 
	struct amdgpu_kiq *kiq;

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;



	switch (adev->asic_type) {

	case CHIP_FIJI:

	case CHIP_TONGA:

	case CHIP_POLARIS11:

	case CHIP_POLARIS12:

	case CHIP_POLARIS10:

	case CHIP_CARRIZO:

		adev->gfx.mec.num_mec = 2;

		break;

	case CHIP_TOPAZ:

	case CHIP_STONEY:

	default:

		adev->gfx.mec.num_mec = 1;

		break;

	}



	adev->gfx.mec.num_pipe_per_mec = 4;

	adev->gfx.mec.num_queue_per_pipe = 8;



	/* KIQ event */

	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 178, &adev->gfx.kiq.irq);

	if (r)

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

+13 −13
Original line number Diff line number Diff line
@@ -870,19 +870,6 @@ static int gfx_v9_0_mec_init(struct amdgpu_device *adev) 


	bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);



	switch (adev->asic_type) {

	case CHIP_VEGA10:

	case CHIP_RAVEN:

		adev->gfx.mec.num_mec = 2;

		break;

	default:

		adev->gfx.mec.num_mec = 1;

		break;

	}



	adev->gfx.mec.num_pipe_per_mec = 4;

	adev->gfx.mec.num_queue_per_pipe = 8;



	/* take ownership of the relevant compute queues */

	amdgpu_gfx_compute_queue_acquire(adev);

	mec_hpd_size = adev->gfx.num_compute_rings * GFX9_MEC_HPD_SIZE;
@@ -1393,6 +1380,19 @@ static int gfx_v9_0_sw_init(void *handle) 
	struct amdgpu_kiq *kiq;

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;



	switch (adev->asic_type) {

	case CHIP_VEGA10:

	case CHIP_RAVEN:

		adev->gfx.mec.num_mec = 2;

		break;

	default:

		adev->gfx.mec.num_mec = 1;

		break;

	}



	adev->gfx.mec.num_pipe_per_mec = 4;

	adev->gfx.mec.num_queue_per_pipe = 8;



	/* KIQ event */

	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 178, &adev->gfx.kiq.irq);

	if (r)