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Commit 4850cf45 authored by Eugenia Emantayev's avatar Eugenia Emantayev Committed by David S. Miller
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net/mlx4_en: Resolve dividing by zero in 32-bit system 



When doing roundup_pow_of_two for large enough number with
bit 31, an overflow will occur and a value equal to 1 will
be returned. In this case 1 will be subtracted from the return
value and division by zero will be reached.

Fixes: 31c128b6 ("net/mlx4_en: Choose time-stamping shift value according to HW frequency")
Signed-off-by: default avatarEugenia Emantayev <eugenia@mellanox.com>
Signed-off-by: default avatarTariq Toukan <tariqt@mellanox.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 72da2e91

drivers/net/ethernet/mellanox/mlx4/en_clock.c

+4 −1
Original line number Diff line number Diff line
@@ -245,8 +245,11 @@ static u32 freq_to_shift(u16 freq) 
{

	u32 freq_khz = freq * 1000;

	u64 max_val_cycles = freq_khz * 1000 * MLX4_EN_WRAP_AROUND_SEC;

	u64 tmp_rounded =

		roundup_pow_of_two(max_val_cycles) > max_val_cycles ?

		roundup_pow_of_two(max_val_cycles) - 1 : UINT_MAX;

	u64 max_val_cycles_rounded = is_power_of_2(max_val_cycles + 1) ?

		max_val_cycles : roundup_pow_of_two(max_val_cycles) - 1;

		max_val_cycles : tmp_rounded;

	/* calculate max possible multiplier in order to fit in 64bit */

	u64 max_mul = div_u64(0xffffffffffffffffULL, max_val_cycles_rounded);