Commit 479c5ae2 authored Jun 21, 2013 by Marc Zyngier Committed by Christoffer Dall Jun 26, 2013

ARM: KVM: add missing dsb before invalidating Stage-2 TLBs



When performing a Stage-2 TLB invalidation, it is necessary to
make sure the write to the page tables is observable by all CPUs.

For this purpose, add a dsb instruction to __kvm_tlb_flush_vmid_ipa
before doing the TLB invalidation itself.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>

parent 6a077e4a

arch/arm/kvm/interrupts.S

+1 −0

Original line number	Diff line number	Diff line
		@@ -49,6 +49,7 @@ __kvm_hyp_code_start:
		ENTRY(__kvm_tlb_flush_vmid_ipa)
		push {r2, r3}

		dsb ishst
		add r0, r0, #KVM_VTTBR
		ldrd r2, r3, [r0]
		mcrr p15, 6, r2, r3, c2 @ Write VTTBR