arm64: Debugging support

/*

 * Copyright (C) 2012 ARM Ltd.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 *

 * You should have received a copy of the GNU General Public License

 * along with this program.  If not, see <http://www.gnu.org/licenses/>.

 */

#ifndef __ASM_DEBUG_MONITORS_H

#define __ASM_DEBUG_MONITORS_H

#ifdef __KERNEL__

#define	DBG_ESR_EVT(x)		(((x) >> 27) & 0x7)

/* AArch64 */

#define DBG_ESR_EVT_HWBP	0x0

#define DBG_ESR_EVT_HWSS	0x1

#define DBG_ESR_EVT_HWWP	0x2

#define DBG_ESR_EVT_BRK		0x6

enum debug_el {

	DBG_ACTIVE_EL0 = 0,

	DBG_ACTIVE_EL1,

};

/* AArch32 */

#define DBG_ESR_EVT_BKPT	0x4

#define DBG_ESR_EVT_VECC	0x5

#define AARCH32_BREAK_ARM	0x07f001f0

#define AARCH32_BREAK_THUMB	0xde01

#define AARCH32_BREAK_THUMB2_LO	0xf7f0

#define AARCH32_BREAK_THUMB2_HI	0xa000

#ifndef __ASSEMBLY__

struct task_struct;

#define local_dbg_save(flags)							\

	do {									\

		typecheck(unsigned long, flags);				\

		asm volatile(							\

		"mrs	%0, daif			// local_dbg_save\n"	\

		"msr	daifset, #8"						\

		: "=r" (flags) : : "memory");					\

	} while (0)

#define local_dbg_restore(flags)						\

	do {									\

		typecheck(unsigned long, flags);				\

		asm volatile(							\

		"msr	daif, %0			// local_dbg_restore\n"	\

		: : "r" (flags) : "memory");					\

	} while (0)

#define DBG_ARCH_ID_RESERVED	0	/* In case of ptrace ABI updates. */

u8 debug_monitors_arch(void);

void enable_debug_monitors(enum debug_el el);

void disable_debug_monitors(enum debug_el el);

void user_rewind_single_step(struct task_struct *task);

void user_fastforward_single_step(struct task_struct *task);

void kernel_enable_single_step(struct pt_regs *regs);

void kernel_disable_single_step(void);

int kernel_active_single_step(void);

#ifdef CONFIG_HAVE_HW_BREAKPOINT

int reinstall_suspended_bps(struct pt_regs *regs);

#else

static inline int reinstall_suspended_bps(struct pt_regs *regs)

{

	return -ENODEV;

}

#endif

#endif	/* __ASSEMBLY */

#endif	/* __KERNEL__ */

#endif	/* __ASM_DEBUG_MONITORS_H */

/*

 * Copyright (C) 2012 ARM Ltd.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 *

 * You should have received a copy of the GNU General Public License

 * along with this program.  If not, see <http://www.gnu.org/licenses/>.

 */

#ifndef __ASM_HW_BREAKPOINT_H

#define __ASM_HW_BREAKPOINT_H

#ifdef __KERNEL__

struct arch_hw_breakpoint_ctrl {

	u32 __reserved	: 19,

	len		: 8,

	type		: 2,

	privilege	: 2,

	enabled		: 1;

};

struct arch_hw_breakpoint {

	u64 address;

	u64 trigger;

	struct arch_hw_breakpoint_ctrl ctrl;

};

static inline u32 encode_ctrl_reg(struct arch_hw_breakpoint_ctrl ctrl)

{

	return (ctrl.len << 5) | (ctrl.type << 3) | (ctrl.privilege << 1) |

		ctrl.enabled;

}

static inline void decode_ctrl_reg(u32 reg,

				   struct arch_hw_breakpoint_ctrl *ctrl)

{

	ctrl->enabled	= reg & 0x1;

	reg >>= 1;

	ctrl->privilege	= reg & 0x3;

	reg >>= 2;

	ctrl->type	= reg & 0x3;

	reg >>= 2;

	ctrl->len	= reg & 0xff;

}

/* Breakpoint */

#define ARM_BREAKPOINT_EXECUTE	0

/* Watchpoints */

#define ARM_BREAKPOINT_LOAD	1

#define ARM_BREAKPOINT_STORE	2

#define AARCH64_ESR_ACCESS_MASK	(1 << 6)

/* Privilege Levels */

#define AARCH64_BREAKPOINT_EL1	1

#define AARCH64_BREAKPOINT_EL0	2

/* Lengths */

#define ARM_BREAKPOINT_LEN_1	0x1

#define ARM_BREAKPOINT_LEN_2	0x3

#define ARM_BREAKPOINT_LEN_4	0xf

#define ARM_BREAKPOINT_LEN_8	0xff

/* Kernel stepping */

#define ARM_KERNEL_STEP_NONE	0

#define ARM_KERNEL_STEP_ACTIVE	1

#define ARM_KERNEL_STEP_SUSPEND	2

/*

 * Limits.

 * Changing these will require modifications to the register accessors.

 */

#define ARM_MAX_BRP		16

#define ARM_MAX_WRP		16

#define ARM_MAX_HBP_SLOTS	(ARM_MAX_BRP + ARM_MAX_WRP)

/* Virtual debug register bases. */

#define AARCH64_DBG_REG_BVR	0

#define AARCH64_DBG_REG_BCR	(AARCH64_DBG_REG_BVR + ARM_MAX_BRP)

#define AARCH64_DBG_REG_WVR	(AARCH64_DBG_REG_BCR + ARM_MAX_BRP)

#define AARCH64_DBG_REG_WCR	(AARCH64_DBG_REG_WVR + ARM_MAX_WRP)

/* Debug register names. */

#define AARCH64_DBG_REG_NAME_BVR	"bvr"

#define AARCH64_DBG_REG_NAME_BCR	"bcr"

#define AARCH64_DBG_REG_NAME_WVR	"wvr"

#define AARCH64_DBG_REG_NAME_WCR	"wcr"

/* Accessor macros for the debug registers. */

#define AARCH64_DBG_READ(N, REG, VAL) do {\

	asm volatile("mrs %0, dbg" REG #N "_el1" : "=r" (VAL));\

} while (0)

#define AARCH64_DBG_WRITE(N, REG, VAL) do {\

	asm volatile("msr dbg" REG #N "_el1, %0" :: "r" (VAL));\

} while (0)

struct task_struct;

struct notifier_block;

struct perf_event;

struct pmu;

extern int arch_bp_generic_fields(struct arch_hw_breakpoint_ctrl ctrl,

				  int *gen_len, int *gen_type);

extern int arch_check_bp_in_kernelspace(struct perf_event *bp);

extern int arch_validate_hwbkpt_settings(struct perf_event *bp);

extern int hw_breakpoint_exceptions_notify(struct notifier_block *unused,

					   unsigned long val, void *data);

extern int arch_install_hw_breakpoint(struct perf_event *bp);

extern void arch_uninstall_hw_breakpoint(struct perf_event *bp);

extern void hw_breakpoint_pmu_read(struct perf_event *bp);

extern int hw_breakpoint_slots(int type);

#ifdef CONFIG_HAVE_HW_BREAKPOINT

extern void hw_breakpoint_thread_switch(struct task_struct *next);

extern void ptrace_hw_copy_thread(struct task_struct *task);

#else

static inline void hw_breakpoint_thread_switch(struct task_struct *next)

{

}

static inline void ptrace_hw_copy_thread(struct task_struct *task)

{

}

#endif

extern struct pmu perf_ops_bp;

#endif	/* __KERNEL__ */

#endif	/* __ASM_BREAKPOINT_H */

/*

 * ARMv8 single-step debug support and mdscr context switching.

 *

 * Copyright (C) 2012 ARM Limited

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 *

 * You should have received a copy of the GNU General Public License

 * along with this program.  If not, see <http://www.gnu.org/licenses/>.

 *

 * Author: Will Deacon <will.deacon@arm.com>

 */

#include <linux/cpu.h>

#include <linux/debugfs.h>

#include <linux/hardirq.h>

#include <linux/init.h>

#include <linux/ptrace.h>

#include <linux/stat.h>

#include <asm/debug-monitors.h>

#include <asm/local.h>

#include <asm/cputype.h>

#include <asm/system_misc.h>

/* Low-level stepping controls. */

#define DBG_MDSCR_SS		(1 << 0)

#define DBG_SPSR_SS		(1 << 21)

/* MDSCR_EL1 enabling bits */

#define DBG_MDSCR_KDE		(1 << 13)

#define DBG_MDSCR_MDE		(1 << 15)

#define DBG_MDSCR_MASK		~(DBG_MDSCR_KDE | DBG_MDSCR_MDE)

/* Determine debug architecture. */

u8 debug_monitors_arch(void)

{

	return read_cpuid(ID_AA64DFR0_EL1) & 0xf;

}

/*

 * MDSCR access routines.

 */

static void mdscr_write(u32 mdscr)

{

	unsigned long flags;

	local_dbg_save(flags);

	asm volatile("msr mdscr_el1, %0" :: "r" (mdscr));

	local_dbg_restore(flags);

}

static u32 mdscr_read(void)

{

	u32 mdscr;

	asm volatile("mrs %0, mdscr_el1" : "=r" (mdscr));

	return mdscr;

}

/*

 * Allow root to disable self-hosted debug from userspace.

 * This is useful if you want to connect an external JTAG debugger.

 */

static u32 debug_enabled = 1;

static int create_debug_debugfs_entry(void)

{

	debugfs_create_bool("debug_enabled", 0644, NULL, &debug_enabled);

	return 0;

}

fs_initcall(create_debug_debugfs_entry);

static int __init early_debug_disable(char *buf)

{

	debug_enabled = 0;

	return 0;

}

early_param("nodebugmon", early_debug_disable);

/*

 * Keep track of debug users on each core.

 * The ref counts are per-cpu so we use a local_t type.

 */

static DEFINE_PER_CPU(local_t, mde_ref_count);

static DEFINE_PER_CPU(local_t, kde_ref_count);

void enable_debug_monitors(enum debug_el el)

{

	u32 mdscr, enable = 0;

	WARN_ON(preemptible());

	if (local_inc_return(&__get_cpu_var(mde_ref_count)) == 1)

		enable = DBG_MDSCR_MDE;

	if (el == DBG_ACTIVE_EL1 &&

	    local_inc_return(&__get_cpu_var(kde_ref_count)) == 1)

		enable |= DBG_MDSCR_KDE;

	if (enable && debug_enabled) {

		mdscr = mdscr_read();

		mdscr |= enable;

		mdscr_write(mdscr);

	}

}

void disable_debug_monitors(enum debug_el el)

{

	u32 mdscr, disable = 0;

	WARN_ON(preemptible());

	if (local_dec_and_test(&__get_cpu_var(mde_ref_count)))

		disable = ~DBG_MDSCR_MDE;

	if (el == DBG_ACTIVE_EL1 &&

	    local_dec_and_test(&__get_cpu_var(kde_ref_count)))

		disable &= ~DBG_MDSCR_KDE;

	if (disable) {

		mdscr = mdscr_read();

		mdscr &= disable;

		mdscr_write(mdscr);

	}

}

/*

 * OS lock clearing.

 */

static void clear_os_lock(void *unused)

{

	asm volatile("msr mdscr_el1, %0" : : "r" (0));

	isb();

	asm volatile("msr oslar_el1, %0" : : "r" (0));

	isb();

}

static int __cpuinit os_lock_notify(struct notifier_block *self,

				    unsigned long action, void *data)

{

	int cpu = (unsigned long)data;

	if (action == CPU_ONLINE)

		smp_call_function_single(cpu, clear_os_lock, NULL, 1);

	return NOTIFY_OK;

}

static struct notifier_block __cpuinitdata os_lock_nb = {

	.notifier_call = os_lock_notify,

};

static int __cpuinit debug_monitors_init(void)

{

	/* Clear the OS lock. */

	smp_call_function(clear_os_lock, NULL, 1);

	clear_os_lock(NULL);

	/* Register hotplug handler. */

	register_cpu_notifier(&os_lock_nb);

	return 0;

}

postcore_initcall(debug_monitors_init);

/*

 * Single step API and exception handling.

 */

static void set_regs_spsr_ss(struct pt_regs *regs)

{

	unsigned long spsr;

	spsr = regs->pstate;

	spsr &= ~DBG_SPSR_SS;

	spsr |= DBG_SPSR_SS;

	regs->pstate = spsr;

}

static void clear_regs_spsr_ss(struct pt_regs *regs)

{

	unsigned long spsr;

	spsr = regs->pstate;

	spsr &= ~DBG_SPSR_SS;

	regs->pstate = spsr;

}

static int single_step_handler(unsigned long addr, unsigned int esr,

			       struct pt_regs *regs)

{

	siginfo_t info;

	/*

	 * If we are stepping a pending breakpoint, call the hw_breakpoint

	 * handler first.

	 */

	if (!reinstall_suspended_bps(regs))

		return 0;

	if (user_mode(regs)) {

		info.si_signo = SIGTRAP;

		info.si_errno = 0;

		info.si_code  = TRAP_HWBKPT;

		info.si_addr  = (void __user *)instruction_pointer(regs);

		force_sig_info(SIGTRAP, &info, current);

		/*

		 * ptrace will disable single step unless explicitly

		 * asked to re-enable it. For other clients, it makes

		 * sense to leave it enabled (i.e. rewind the controls

		 * to the active-not-pending state).

		 */

		user_rewind_single_step(current);

	} else {

		/* TODO: route to KGDB */

		pr_warning("Unexpected kernel single-step exception at EL1\n");

		/*

		 * Re-enable stepping since we know that we will be

		 * returning to regs.

		 */

		set_regs_spsr_ss(regs);

	}

	return 0;

}

static int __init single_step_init(void)

{

	hook_debug_fault_code(DBG_ESR_EVT_HWSS, single_step_handler, SIGTRAP,

			      TRAP_HWBKPT, "single-step handler");

	return 0;

}

arch_initcall(single_step_init);

/* Re-enable single step for syscall restarting. */

void user_rewind_single_step(struct task_struct *task)

{

	/*

	 * If single step is active for this thread, then set SPSR.SS

	 * to 1 to avoid returning to the active-pending state.

	 */

	if (test_ti_thread_flag(task_thread_info(task), TIF_SINGLESTEP))

		set_regs_spsr_ss(task_pt_regs(task));

}

void user_fastforward_single_step(struct task_struct *task)

{

	if (test_ti_thread_flag(task_thread_info(task), TIF_SINGLESTEP))

		clear_regs_spsr_ss(task_pt_regs(task));

}

/* Kernel API */

void kernel_enable_single_step(struct pt_regs *regs)

{

	WARN_ON(!irqs_disabled());

	set_regs_spsr_ss(regs);

	mdscr_write(mdscr_read() | DBG_MDSCR_SS);

	enable_debug_monitors(DBG_ACTIVE_EL1);

}

void kernel_disable_single_step(void)

{

	WARN_ON(!irqs_disabled());

	mdscr_write(mdscr_read() & ~DBG_MDSCR_SS);

	disable_debug_monitors(DBG_ACTIVE_EL1);

}

int kernel_active_single_step(void)

{

	WARN_ON(!irqs_disabled());

	return mdscr_read() & DBG_MDSCR_SS;

}

/* ptrace API */

void user_enable_single_step(struct task_struct *task)

{

	set_ti_thread_flag(task_thread_info(task), TIF_SINGLESTEP);

	set_regs_spsr_ss(task_pt_regs(task));

}

void user_disable_single_step(struct task_struct *task)

{

	clear_ti_thread_flag(task_thread_info(task), TIF_SINGLESTEP);

}