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Commit 46dd2e28 authored by Chris Zhong's avatar Chris Zhong Committed by Mark Brown
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ASoC: rockchip: correct the spdif clk 



The spdif mclk should be 128 times of sample rate, and there is a
internal divider, the real rate of spdif mclk is mclk / (div + 1).
Hence, the original driver always get the good frequency for
48000/96000/44100/192000. But for 32000, the mclk is incorrect,
it should be 32000*128, but get 48000*128. Do not use the internal
divider here, just set all mclk to 128 * sample rate directly.

Signed-off-by: default avatarChris Zhong <zyw@rock-chips.com>
Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent 359d9abd

sound/soc/rockchip/rockchip_spdif.c

+1 −16
Original line number Diff line number Diff line
@@ -101,21 +101,7 @@ static int rk_spdif_hw_params(struct snd_pcm_substream *substream, 
	int ret;



	srate = params_rate(params);

	switch (srate) {

	case 32000:

	case 48000:

	case 96000:

		mclk = 96000 * 128; /* 12288000 hz */

		break;

	case 44100:

		mclk = 44100 * 256; /* 11289600 hz */

		break;

	case 192000:

		mclk = 192000 * 128; /* 24576000 hz */

		break;

	default:

		return -EINVAL;

	}

	mclk = srate * 128;



	switch (params_format(params)) {

	case SNDRV_PCM_FORMAT_S16_LE:
@@ -139,7 +125,6 @@ static int rk_spdif_hw_params(struct snd_pcm_substream *substream, 
		return ret;

	}



	val |= SPDIF_CFGR_CLK_DIV(mclk/(srate * 256));

	ret = regmap_update_bits(spdif->regmap, SPDIF_CFGR,

		SPDIF_CFGR_CLK_DIV_MASK | SPDIF_CFGR_HALFWORD_ENABLE |

		SDPIF_CFGR_VDW_MASK,