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Commit 46c06a30 authored by Ville Syrjälä's avatar Ville Syrjälä Committed by Daniel Vetter
Browse files

drm/i915: Kill pipestat[] cache 



Caching the PIPESTAT enable bits has been deemed pointless. Just
read them from the register itself.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 90a72f87

drivers/gpu/drm/i915/i915_drv.h

+0 −1
Original line number Diff line number Diff line
@@ -905,7 +905,6 @@ typedef struct drm_i915_private { 
	struct mutex dpio_lock;



	/** Cached value of IMR to avoid reads in updating the bitfield */

	u32 pipestat[2];

	u32 irq_mask;

	u32 gt_irq_mask;

drivers/gpu/drm/i915/i915_irq.c

+17 −24
Original line number Diff line number Diff line
@@ -60,27 +60,31 @@ ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask) 
void

i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)

{

	if ((dev_priv->pipestat[pipe] & mask) != mask) {

	u32 reg = PIPESTAT(pipe);

	u32 pipestat = I915_READ(reg) & 0x7fff0000;



	if ((pipestat & mask) == mask)

		return;



		dev_priv->pipestat[pipe] |= mask;

	/* Enable the interrupt, clear any pending status */

		I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));

	pipestat |= mask | (mask >> 16);

	I915_WRITE(reg, pipestat);

	POSTING_READ(reg);

}

}



void

i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)

{

	if ((dev_priv->pipestat[pipe] & mask) != 0) {

	u32 reg = PIPESTAT(pipe);

	u32 pipestat = I915_READ(reg) & 0x7fff0000;



	if ((pipestat & mask) == 0)

		return;



		dev_priv->pipestat[pipe] &= ~mask;

		I915_WRITE(reg, dev_priv->pipestat[pipe]);

	pipestat &= ~mask;

	I915_WRITE(reg, pipestat);

	POSTING_READ(reg);

}

}



/**

 * intel_enable_asle - enable ASLE interrupt for OpRegion
@@ -2069,9 +2073,6 @@ static int valleyview_irq_postinstall(struct drm_device *dev) 
		I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |

		I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;



	dev_priv->pipestat[0] = 0;

	dev_priv->pipestat[1] = 0;



	/* Hack for broken MSIs on VLV */

	pci_write_config_dword(dev_priv->dev->pdev, 0x94, 0xfee00000);

	pci_read_config_word(dev->pdev, 0x98, &msid);
@@ -2201,9 +2202,6 @@ static int i8xx_irq_postinstall(struct drm_device *dev) 
{

	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;



	dev_priv->pipestat[0] = 0;

	dev_priv->pipestat[1] = 0;



	I915_WRITE16(EMR,

		     ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
@@ -2365,9 +2363,6 @@ static int i915_irq_postinstall(struct drm_device *dev) 
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;

	u32 enable_mask;



	dev_priv->pipestat[0] = 0;

	dev_priv->pipestat[1] = 0;



	I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));



	/* Unmask the interrupts that we always want on. */
@@ -2634,8 +2629,6 @@ static int i965_irq_postinstall(struct drm_device *dev) 
	if (IS_G4X(dev))

		enable_mask |= I915_BSD_USER_INTERRUPT;



	dev_priv->pipestat[0] = 0;

	dev_priv->pipestat[1] = 0;

	i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);



	/*