Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 465ac0c6 authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915: Define VLV/CHV display power well domains properly 



Currently we're using POWER_DOMAIN_MASK as the power domains for the
display power well on VLV/CHV. That includes all power domains even
though the disp2d/pipe-a power well is not needed for a lot of things.
Let's reduce these to what we actually need.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1460977348-32260-3-git-send-email-ville.syrjala@linux.intel.com


Reviewed-by: default avatarImre Deak <imre.deak@intel.com>
parent 998bd66a

drivers/gpu/drm/i915/intel_runtime_pm.c

+40 −2
Original line number Diff line number Diff line
@@ -1618,7 +1618,23 @@ void intel_display_power_put(struct drm_i915_private *dev_priv, 
	(POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS) |	\

	BIT(POWER_DOMAIN_INIT))



#define VLV_DISPLAY_POWER_DOMAINS	POWER_DOMAIN_MASK

#define VLV_DISPLAY_POWER_DOMAINS (		\

	BIT(POWER_DOMAIN_PIPE_A) |		\

	BIT(POWER_DOMAIN_PIPE_B) |		\

	BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) |	\

	BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |	\

	BIT(POWER_DOMAIN_TRANSCODER_A) |	\

	BIT(POWER_DOMAIN_TRANSCODER_B) |	\

	BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |	\

	BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |	\

	BIT(POWER_DOMAIN_PORT_DSI) |		\

	BIT(POWER_DOMAIN_PORT_CRT) |		\

	BIT(POWER_DOMAIN_VGA) |			\

	BIT(POWER_DOMAIN_AUDIO) |		\

	BIT(POWER_DOMAIN_AUX_B) |		\

	BIT(POWER_DOMAIN_AUX_C) |		\

	BIT(POWER_DOMAIN_GMBUS) |		\

	BIT(POWER_DOMAIN_INIT))



#define VLV_DPIO_CMN_BC_POWER_DOMAINS (		\

	BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |	\
@@ -1648,6 +1664,28 @@ void intel_display_power_put(struct drm_i915_private *dev_priv, 
	BIT(POWER_DOMAIN_AUX_C) |		\

	BIT(POWER_DOMAIN_INIT))



#define CHV_DISPLAY_POWER_DOMAINS (		\

	BIT(POWER_DOMAIN_PIPE_A) |		\

	BIT(POWER_DOMAIN_PIPE_B) |		\

	BIT(POWER_DOMAIN_PIPE_C) |		\

	BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) |	\

	BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |	\

	BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |	\

	BIT(POWER_DOMAIN_TRANSCODER_A) |	\

	BIT(POWER_DOMAIN_TRANSCODER_B) |	\

	BIT(POWER_DOMAIN_TRANSCODER_C) |	\

	BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |	\

	BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |	\

	BIT(POWER_DOMAIN_PORT_DDI_D_LANES) |	\

	BIT(POWER_DOMAIN_PORT_DSI) |		\

	BIT(POWER_DOMAIN_VGA) |			\

	BIT(POWER_DOMAIN_AUDIO) |		\

	BIT(POWER_DOMAIN_AUX_B) |		\

	BIT(POWER_DOMAIN_AUX_C) |		\

	BIT(POWER_DOMAIN_AUX_D) |		\

	BIT(POWER_DOMAIN_GMBUS) |		\

	BIT(POWER_DOMAIN_INIT))



#define CHV_DPIO_CMN_BC_POWER_DOMAINS (		\

	BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |	\

	BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |	\
@@ -1832,7 +1870,7 @@ static struct i915_power_well chv_power_wells[] = { 
		 * power wells don't actually exist. Pipe A power well is

		 * required for any pipe to work.

		 */

		.domains = VLV_DISPLAY_POWER_DOMAINS,

		.domains = CHV_DISPLAY_POWER_DOMAINS,

		.data = PIPE_A,

		.ops = &chv_pipe_power_well_ops,

	},