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Commit 45c480b5 authored by Greg Kroah-Hartman's avatar Greg Kroah-Hartman
Browse files

Merge 4.19.216 into android-4.19-stable 



Changes in 4.19.216
	scsi: core: Put LLD module refcnt after SCSI device is released
	media: firewire: firedtv-avc: fix a buffer overflow in avc_ca_pmt()
	IB/qib: Use struct_size() helper
	IB/qib: Protect from buffer overflow in struct qib_user_sdma_pkt fields
	sfc: Fix reading non-legacy supported link modes
	arch: pgtable: define MAX_POSSIBLE_PHYSMEM_BITS where needed
	ARM: 9120/1: Revert "amba: make use of -1 IRQs warn"
	Linux 4.19.216

Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@google.com>
Change-Id: I64effccc85e57b1850ba7139177282da9b122929
parents 65de976f 3033e572

Makefile

+1 −1
Original line number Diff line number Diff line 
# SPDX-License-Identifier: GPL-2.0

VERSION = 4

PATCHLEVEL = 19

SUBLEVEL = 215

SUBLEVEL = 216

EXTRAVERSION =

NAME = "People's Front"

arch/arc/include/asm/pgtable.h

+2 −0
Original line number Diff line number Diff line
@@ -138,8 +138,10 @@ 


#ifdef CONFIG_ARC_HAS_PAE40

#define PTE_BITS_NON_RWX_IN_PD1	(0xff00000000 | PAGE_MASK | _PAGE_CACHEABLE)

#define MAX_POSSIBLE_PHYSMEM_BITS 40

#else

#define PTE_BITS_NON_RWX_IN_PD1	(PAGE_MASK | _PAGE_CACHEABLE)

#define MAX_POSSIBLE_PHYSMEM_BITS 32

#endif



/**************************************************************************

arch/arm/include/asm/pgtable-2level.h

+2 −0
Original line number Diff line number Diff line
@@ -78,6 +78,8 @@ 
#define PTE_HWTABLE_OFF		(PTE_HWTABLE_PTRS * sizeof(pte_t))

#define PTE_HWTABLE_SIZE	(PTRS_PER_PTE * sizeof(u32))



#define MAX_POSSIBLE_PHYSMEM_BITS	32



/*

 * PMD_SHIFT determines the size of the area a second-level page table can map

 * PGDIR_SHIFT determines what a third-level page table entry can map

arch/arm/include/asm/pgtable-3level.h

+2 −0
Original line number Diff line number Diff line
@@ -37,6 +37,8 @@ 
#define PTE_HWTABLE_OFF		(0)

#define PTE_HWTABLE_SIZE	(PTRS_PER_PTE * sizeof(u64))



#define MAX_POSSIBLE_PHYSMEM_BITS 40



/*

 * PGDIR_SHIFT determines the size a top-level page table entry can map.

 */

arch/mips/include/asm/pgtable-32.h

+3 −0
Original line number Diff line number Diff line
@@ -111,6 +111,7 @@ static inline void pmd_clear(pmd_t *pmdp) 


#if defined(CONFIG_XPA)



#define MAX_POSSIBLE_PHYSMEM_BITS 40

#define pte_pfn(x)		(((unsigned long)((x).pte_high >> _PFN_SHIFT)) | (unsigned long)((x).pte_low << _PAGE_PRESENT_SHIFT))

static inline pte_t

pfn_pte(unsigned long pfn, pgprot_t prot)
@@ -126,6 +127,7 @@ pfn_pte(unsigned long pfn, pgprot_t prot) 


#elif defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)



#define MAX_POSSIBLE_PHYSMEM_BITS 36

#define pte_pfn(x)		((unsigned long)((x).pte_high >> 6))



static inline pte_t pfn_pte(unsigned long pfn, pgprot_t prot)
@@ -140,6 +142,7 @@ static inline pte_t pfn_pte(unsigned long pfn, pgprot_t prot) 


#else



#define MAX_POSSIBLE_PHYSMEM_BITS 32

#ifdef CONFIG_CPU_VR41XX

#define pte_pfn(x)		((unsigned long)((x).pte >> (PAGE_SHIFT + 2)))

#define pfn_pte(pfn, prot)	__pte(((pfn) << (PAGE_SHIFT + 2)) | pgprot_val(prot))