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Commit 45949ebe authored by Aneesh Kumar K.V's avatar Aneesh Kumar K.V Committed by Michael Ellerman
Browse files

powerpc/nohash: we don't use real_pte_t for nohash 



Remove the related functions and #defines

Signed-off-by: default avatarAneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
parent cc50380d

arch/powerpc/include/asm/nohash/64/pgtable.h

+0 −33
Original line number Original line Diff line number Diff line
@@ -106,39 +106,6 @@ 
#endif /* CONFIG_PPC_MM_SLICES */

#endif /* CONFIG_PPC_MM_SLICES */





#ifndef __ASSEMBLY__

#ifndef __ASSEMBLY__



/*

 * This is the default implementation of various PTE accessors, it's

 * used in all cases except Book3S with 64K pages where we have a

 * concept of sub-pages

 */

#ifndef __real_pte



#ifdef CONFIG_STRICT_MM_TYPECHECKS

#define __real_pte(e,p)		((real_pte_t){(e)})

#define __rpte_to_pte(r)	((r).pte)

#else

#define __real_pte(e,p)		(e)

#define __rpte_to_pte(r)	(__pte(r))

#endif

#define __rpte_to_hidx(r,index)	(pte_val(__rpte_to_pte(r)) >> _PAGE_F_GIX_SHIFT)



#define pte_iterate_hashed_subpages(rpte, psize, va, index, shift)       \

	do {							         \

		index = 0;					         \

		shift = mmu_psize_defs[psize].shift;		         \



#define pte_iterate_hashed_end() } while(0)



/*

 * We expect this to be called only for user addresses or kernel virtual

 * addresses other than the linear mapping.

 */

#define pte_pagesize_index(mm, addr, pte)	MMU_PAGE_4K



#endif /* __real_pte */





/* pte_clear moved to later in this file */

/* pte_clear moved to later in this file */





#define PMD_BAD_BITS		(PTE_TABLE_SIZE-1)

#define PMD_BAD_BITS		(PTE_TABLE_SIZE-1)