Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 457c2403 authored by Ben Dooks's avatar Ben Dooks
Browse files

ARM: asm: Add ARM_BE8() assembly helper 



Add ARM_BE8() helper to wrap any code conditional on being
compile when CONFIG_ARM_ENDIAN_BE8 is selected and convert
existing places where this is to use it.

Acked-by: default avatarNicolas Pitre <nico@linaro.org>
Reviewed-by: default avatarWill Deacon <will.deacon@arm.com>
Signed-off-by: default avatarBen Dooks <ben.dooks@codethink.co.uk>
parent d10d2d48

arch/arm/boot/compressed/head.S

+2 −6
Original line number Diff line number Diff line
@@ -699,9 +699,7 @@ __armv4_mmu_cache_on: 
		mrc	p15, 0, r0, c1, c0, 0	@ read control reg

		orr	r0, r0, #0x5000		@ I-cache enable, RR cache replacement

		orr	r0, r0, #0x0030

#ifdef CONFIG_CPU_ENDIAN_BE8

		orr	r0, r0, #1 << 25	@ big-endian page tables

#endif

 ARM_BE8(	orr	r0, r0, #1 << 25 )	@ big-endian page tables

		bl	__common_mmu_cache_on

		mov	r0, #0

		mcr	p15, 0, r0, c8, c7, 0	@ flush I,D TLBs
@@ -728,9 +726,7 @@ __armv7_mmu_cache_on: 
		orr	r0, r0, #1 << 22	@ U (v6 unaligned access model)

						@ (needed for ARM1176)

#ifdef CONFIG_MMU

#ifdef CONFIG_CPU_ENDIAN_BE8

		orr	r0, r0, #1 << 25	@ big-endian page tables

#endif

 ARM_BE8(	orr	r0, r0, #1 << 25 )	@ big-endian page tables

		mrcne   p15, 0, r6, c2, c0, 2   @ read ttb control reg

		orrne	r0, r0, #1		@ MMU enabled

		movne	r1, #0xfffffffd		@ domain 0 = client

arch/arm/include/asm/assembler.h

+7 −0
Original line number Diff line number Diff line
@@ -53,6 +53,13 @@ 
#define put_byte_3      lsl #0

#endif



/* Select code for any configuration running in BE8 mode */

#ifdef CONFIG_CPU_ENDIAN_BE8

#define ARM_BE8(code...) code

#else

#define ARM_BE8(code...)

#endif



/*

 * Data preload for architectures that support it

 */

arch/arm/kernel/entry-armv.S

+2 −3
Original line number Diff line number Diff line
@@ -416,9 +416,8 @@ __und_usr: 
	bne	__und_usr_thumb

	sub	r4, r2, #4			@ ARM instr at LR - 4

1:	ldrt	r0, [r4]

#ifdef CONFIG_CPU_ENDIAN_BE8

	rev	r0, r0				@ little endian instruction

#endif

 ARM_BE8(rev	r0, r0)				@ little endian instruction



	@ r0 = 32-bit ARM instruction which caused the exception

	@ r2 = PC value for the following instruction (:= regs->ARM_pc)

	@ r4 = PC value for the faulting instruction

arch/arm/kernel/entry-common.S

+1 −3
Original line number Diff line number Diff line
@@ -393,9 +393,7 @@ ENTRY(vector_swi) 
#else

 USER(	ldr	r10, [lr, #-4]		)	@ get SWI instruction

#endif

#ifdef CONFIG_CPU_ENDIAN_BE8

	rev	r10, r10			@ little endian instruction

#endif

 ARM_BE8(rev	r10, r10)			@ little endian instruction



#elif defined(CONFIG_AEABI)

arch/arm/mm/abort-ev6.S

+2 −3
Original line number Diff line number Diff line
@@ -38,9 +38,8 @@ ENTRY(v6_early_abort) 
	bne	do_DataAbort

	bic	r1, r1, #1 << 11		@ clear bit 11 of FSR

	ldr	r3, [r4]			@ read aborted ARM instruction

#ifdef CONFIG_CPU_ENDIAN_BE8

	rev	r3, r3

#endif

 ARM_BE8(rev	r3, r3)



	do_ldrd_abort tmp=ip, insn=r3

	tst	r3, #1 << 20			@ L = 0 -> write

	orreq	r1, r1, #1 << 11		@ yes.