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Commit 44991eb4 authored by Jisheng Zhang's avatar Jisheng Zhang Committed by Sebastian Hesselbarth
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ARM: dts: berlin2q: set L2CC tag and data latency to 2 cycles 



For all BG2Q SoCs, 2 cycles is the best/correct value.

Signed-off-by: default avatarJisheng Zhang <jszhang@marvell.com>
Signed-off-by: default avatarSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
parent 7171511e

arch/arm/boot/dts/berlin2q.dtsi

+2 −0
Original line number Diff line number Diff line
@@ -90,6 +90,8 @@ 
			compatible = "arm,pl310-cache";

			reg = <0xac0000 0x1000>;

			cache-level = <2>;

			arm,data-latency = <2 2 2>;

			arm,tag-latency = <2 2 2>;

		};



		scu: snoop-control-unit@ad0000 {