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Commit 44913155 authored by Ville Syrjälä's avatar Ville Syrjälä Committed by Jani Nikula
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drm/i915: Store max cdclk value in dev_priv 



Keep the cdclk maximum supported frequency around in dev_priv so that we
can verify certain things against it before actually changing the cdclk
frequency.

For now only VLV/CHV have support changing cdclk frequency, so other
plarforms get to assume cdclk is fixed.

v2: Rebased to the latest
v3: Rebased to the latest
v4: Fix for patch style problems

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarMika Kahola <mika.kahola@intel.com>
Reviewed-by: default avatarDamien Lespiau <damien.lespiau@intel.com>
Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
parent 05024da3

drivers/gpu/drm/i915/i915_drv.h

+1 −1
Original line number Diff line number Diff line
@@ -1743,7 +1743,7 @@ struct drm_i915_private { 


	unsigned int fsb_freq, mem_freq, is_ddr3;

	unsigned int skl_boot_cdclk;

	unsigned int cdclk_freq;

	unsigned int cdclk_freq, max_cdclk_freq;

	unsigned int hpll_freq;



	/**

drivers/gpu/drm/i915/intel_display.c

+19 −1
Original line number Diff line number Diff line
@@ -5747,6 +5747,21 @@ static int valleyview_get_vco(struct drm_i915_private *dev_priv) 
	return vco_freq[hpll_freq] * 1000;

}



static void intel_update_max_cdclk(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = dev->dev_private;



	if (IS_VALLEYVIEW(dev)) {

		dev_priv->max_cdclk_freq = 400000;

	} else {

		/* otherwise assume cdclk is fixed */

		dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;

	}



	DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",

			 dev_priv->max_cdclk_freq);

}



static void intel_update_cdclk(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -5768,6 +5783,9 @@ static void intel_update_cdclk(struct drm_device *dev) 
		 */

		I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));

	}



	if (dev_priv->max_cdclk_freq == 0)

		intel_update_max_cdclk(dev);

}



/* Adjust CDclk dividers to allow high res or save power if possible */
@@ -6610,7 +6628,7 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc, 


	/* FIXME should check pixel clock limits on all platforms */

	if (INTEL_INFO(dev)->gen < 4) {

		int clock_limit = dev_priv->cdclk_freq;

		int clock_limit = dev_priv->max_cdclk_freq;



		/*

		 * Enable pixel doubling when the dot clock