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Commit 442e14a2 authored by Steven J. Hill's avatar Steven J. Hill Committed by Ralf Baechle
Browse files

MIPS: Add 1074K CPU support explicitly. 



The 1074K is a multiprocessing coherent processing system (CPS) based
on modified 74K cores. This patch makes the 1074K an actual unique
CPU type, instead of a 74K derivative, which it is not.

Signed-off-by: default avatarSteven J. Hill <Steven.Hill@imgtec.com>
Reviewed-by: default avatarLeonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6389/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 02dc6bfb

arch/mips/bcm47xx/setup.c

+1 −1
Original line number Diff line number Diff line
@@ -212,7 +212,7 @@ void __init plat_mem_setup(void) 
{

	struct cpuinfo_mips *c = &current_cpu_data;



	if (c->cputype == CPU_74K) {

	if ((c->cputype == CPU_74K) || (c->cputype == CPU_1074K)) {

		printk(KERN_INFO "bcm47xx: using bcma bus\n");

#ifdef CONFIG_BCM47XX_BCMA

		bcm47xx_bus_type = BCM47XX_BUS_TYPE_BCMA;

arch/mips/include/asm/cpu.h

+1 −1
Original line number Diff line number Diff line
@@ -296,7 +296,7 @@ enum cpu_type_enum { 
	CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K,

	CPU_ALCHEMY, CPU_PR4450, CPU_BMIPS32, CPU_BMIPS3300, CPU_BMIPS4350,

	CPU_BMIPS4380, CPU_BMIPS5000, CPU_JZRISC, CPU_LOONGSON1, CPU_M14KC,

	CPU_M14KEC, CPU_INTERAPTIV, CPU_PROAPTIV,

	CPU_M14KEC, CPU_INTERAPTIV, CPU_PROAPTIV, CPU_1074K,



	/*

	 * MIPS64 class processors

arch/mips/kernel/cpu-probe.c

+1 −1
Original line number Diff line number Diff line
@@ -806,7 +806,7 @@ static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu) 
		__cpu_name[cpu] = "MIPS 1004Kc";

		break;

	case PRID_IMP_1074K:

		c->cputype = CPU_74K;

		c->cputype = CPU_1074K;

		__cpu_name[cpu] = "MIPS 1074Kc";

		break;

	case PRID_IMP_INTERAPTIV_UP:

arch/mips/kernel/idle.c

+1 −0
Original line number Diff line number Diff line
@@ -184,6 +184,7 @@ void __init check_wait(void) 
	case CPU_24K:

	case CPU_34K:

	case CPU_1004K:

	case CPU_1074K:

	case CPU_INTERAPTIV:

	case CPU_PROAPTIV:

		cpu_wait = r4k_wait;

arch/mips/kernel/perf_event_mipsxx.c

+6 −0
Original line number Diff line number Diff line
@@ -1442,6 +1442,7 @@ static const struct mips_perf_event *mipsxx_pmu_map_raw_event(u64 config) 
#endif

		break;

	case CPU_74K:

	case CPU_1074K:

		if (IS_BOTH_COUNTERS_74K_EVENT(base_id))

			raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;

		else
@@ -1584,6 +1585,11 @@ init_hw_perf_events(void) 
		mipspmu.general_event_map = &mipsxxcore_event_map;

		mipspmu.cache_event_map = &mipsxxcore_cache_map;

		break;

	case CPU_1074K:

		mipspmu.name = "mips/1074K";

		mipspmu.general_event_map = &mipsxxcore_event_map;

		mipspmu.cache_event_map = &mipsxxcore_cache_map;

		break;

	case CPU_LOONGSON1:

		mipspmu.name = "mips/loongson1";

		mipspmu.general_event_map = &mipsxxcore_event_map;