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Commit 441ad741 authored by Eric Yang's avatar Eric Yang Committed by Alex Deucher
Browse files

drm/amd/display: Add override for reporting wm ranges 



For verification of watermark select with SMU team, proper
implementation will follow

Signed-off-by: default avatarEric Yang <Eric.Yang2@amd.com>
Reviewed-by: default avatarTony Cheng <Tony.Cheng@amd.com>
Acked-by: default avatarHarry Wentland <Harry.Wentland@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent dcf298c3

drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c

+47 −0
Original line number Diff line number Diff line
@@ -1441,6 +1441,53 @@ void dcn_bw_notify_pplib_of_wm_ranges(struct dc *dc) 
	ranges.writer_wm_sets[3].min_drain_clk_khz = max_fclk_khz;

	ranges.writer_wm_sets[3].max_drain_clk_khz = max_fclk_khz;



	if (dc->debug.pplib_wm_report_mode == WM_REPORT_OVERRIDE) {

		ranges.reader_wm_sets[0].wm_inst = WM_A;

		ranges.reader_wm_sets[0].min_drain_clk_khz = 300000;

		ranges.reader_wm_sets[0].max_drain_clk_khz = 654000;

		ranges.reader_wm_sets[0].min_fill_clk_khz = 800000;

		ranges.reader_wm_sets[0].max_fill_clk_khz = 800000;

		ranges.writer_wm_sets[0].wm_inst = WM_A;

		ranges.writer_wm_sets[0].min_fill_clk_khz = 200000;

		ranges.writer_wm_sets[0].max_fill_clk_khz = 757000;

		ranges.writer_wm_sets[0].min_drain_clk_khz = 800000;

		ranges.writer_wm_sets[0].max_drain_clk_khz = 800000;



		ranges.reader_wm_sets[1].wm_inst = WM_B;

		ranges.reader_wm_sets[1].min_drain_clk_khz = 300000;

		ranges.reader_wm_sets[1].max_drain_clk_khz = 654000;

		ranges.reader_wm_sets[1].min_fill_clk_khz = 933000;

		ranges.reader_wm_sets[1].max_fill_clk_khz = 933000;

		ranges.writer_wm_sets[1].wm_inst = WM_B;

		ranges.writer_wm_sets[1].min_fill_clk_khz = 200000;

		ranges.writer_wm_sets[1].max_fill_clk_khz = 757000;

		ranges.writer_wm_sets[1].min_drain_clk_khz = 933000;

		ranges.writer_wm_sets[1].max_drain_clk_khz = 933000;





		ranges.reader_wm_sets[2].wm_inst = WM_C;

		ranges.reader_wm_sets[2].min_drain_clk_khz = 300000;

		ranges.reader_wm_sets[2].max_drain_clk_khz = 654000;

		ranges.reader_wm_sets[2].min_fill_clk_khz = 1067000;

		ranges.reader_wm_sets[2].max_fill_clk_khz = 1067000;

		ranges.writer_wm_sets[2].wm_inst = WM_C;

		ranges.writer_wm_sets[2].min_fill_clk_khz = 200000;

		ranges.writer_wm_sets[2].max_fill_clk_khz = 757000;

		ranges.writer_wm_sets[2].min_drain_clk_khz = 1067000;

		ranges.writer_wm_sets[2].max_drain_clk_khz = 1067000;



		ranges.reader_wm_sets[3].wm_inst = WM_D;

		ranges.reader_wm_sets[3].min_drain_clk_khz = 300000;

		ranges.reader_wm_sets[3].max_drain_clk_khz = 654000;

		ranges.reader_wm_sets[3].min_fill_clk_khz = 1200000;

		ranges.reader_wm_sets[3].max_fill_clk_khz = 1200000;

		ranges.writer_wm_sets[3].wm_inst = WM_D;

		ranges.writer_wm_sets[3].min_fill_clk_khz = 200000;

		ranges.writer_wm_sets[3].max_fill_clk_khz = 757000;

		ranges.writer_wm_sets[3].min_drain_clk_khz = 1200000;

		ranges.writer_wm_sets[3].max_drain_clk_khz = 1200000;

	}



	/* Notify PP Lib/SMU which Watermarks to use for which clock ranges */

	pp->set_wm_ranges(&pp->pp_smu, &ranges);

}

drivers/gpu/drm/amd/display/dc/dc.h

+6 −0
Original line number Diff line number Diff line
@@ -173,6 +173,11 @@ enum pipe_split_policy { 
	MPC_SPLIT_AVOID_MULT_DISP = 2,

};



enum wm_report_mode {

	WM_REPORT_DEFAULT = 0,

	WM_REPORT_OVERRIDE = 1,

};



struct dc_debug {

	bool surface_visual_confirm;

	bool sanity_checks;
@@ -194,6 +199,7 @@ struct dc_debug { 
	bool disable_dpp_power_gate;

	bool disable_hubp_power_gate;

	bool disable_pplib_wm_range;

	enum wm_report_mode pplib_wm_report_mode;

	bool use_dml_wm;

	unsigned int min_disp_clk_khz;

	int sr_exit_time_dpm0_ns;

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

+3 −0
Original line number Diff line number Diff line
@@ -2451,6 +2451,9 @@ static void optimize_shared_resources(struct dc *dc) 
		/* S0i2 message */

		dcn10_pplib_apply_display_requirements(dc, dc->current_state);

	}



	if (dc->debug.pplib_wm_report_mode == WM_REPORT_OVERRIDE)

		dcn_bw_notify_pplib_of_wm_ranges(dc);

}



static void ready_shared_resources(struct dc *dc, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c

+1 −0
Original line number Diff line number Diff line
@@ -424,6 +424,7 @@ static const struct dc_debug debug_defaults_drv = { 


		.disable_pplib_clock_request = true,

		.disable_pplib_wm_range = false,

		.pplib_wm_report_mode = WM_REPORT_DEFAULT,

		.use_dml_wm = false,



		.pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP,