Loading drivers/net/wireless/cnss2/pci.c +41 −0 Original line number Diff line number Diff line Loading @@ -130,6 +130,13 @@ static struct cnss_pci_reg qdss_csr[] = { { NULL }, }; static struct cnss_pci_reg pci_scratch[] = { { "PCIE_SCRATCH_0", PCIE_SCRATCH_0_SOC_PCIE_REG }, { "PCIE_SCRATCH_1", PCIE_SCRATCH_1_SOC_PCIE_REG }, { "PCIE_SCRATCH_2", PCIE_SCRATCH_2_SOC_PCIE_REG }, { NULL }, }; static struct cnss_misc_reg wcss_reg_access_seq[] = { {0, QCA6390_GCC_DEBUG_CLK_CTL, 0}, {1, QCA6390_GCC_DEBUG_CLK_CTL, 0x802}, Loading Loading @@ -722,6 +729,35 @@ static int cnss_set_pci_link(struct cnss_pci_data *pci_priv, bool link_up) return ret; } static void cnss_pci_soc_scratch_reg_dump(struct cnss_pci_data *pci_priv) { u32 reg_offset, val; int i; switch (pci_priv->device_id) { case QCA6490_DEVICE_ID: break; default: return; } if (in_interrupt() || irqs_disabled()) return; if (cnss_pci_check_link_status(pci_priv)) return; cnss_pr_dbg("Start to dump SOC Scratch registers\n"); for (i = 0; pci_scratch[i].name; i++) { reg_offset = pci_scratch[i].offset; if (cnss_pci_reg_read(pci_priv, reg_offset, &val)) return; cnss_pr_dbg("PCIE_SOC_REG_%s = 0x%x\n", pci_scratch[i].name, val); } } int cnss_suspend_pci_link(struct cnss_pci_data *pci_priv) { int ret = 0; Loading Loading @@ -841,6 +877,7 @@ int cnss_pci_recover_link_down(struct cnss_pci_data *pci_priv) jiffies + msecs_to_jiffies(DEV_RDDM_TIMEOUT)); mhi_debug_reg_dump(pci_priv->mhi_ctrl); cnss_pci_soc_scratch_reg_dump(pci_priv); return 0; } Loading Loading @@ -1758,6 +1795,7 @@ static void cnss_pci_dump_misc_reg(struct cnss_pci_data *pci_priv) return; mhi_debug_reg_dump(pci_priv->mhi_ctrl); cnss_pci_soc_scratch_reg_dump(pci_priv); cnss_pci_misc_reg_dump(pci_priv, pci_priv->wcss_reg, pci_priv->wcss_reg_size, "wcss"); cnss_pci_misc_reg_dump(pci_priv, pci_priv->pcie_reg, Loading @@ -1775,6 +1813,7 @@ static void cnss_pci_dump_mhi_reg(struct cnss_pci_data *pci_priv) return; mhi_debug_reg_dump(pci_priv->mhi_ctrl); cnss_pci_soc_scratch_reg_dump(pci_priv); } static void cnss_pci_dump_shadow_reg(struct cnss_pci_data *pci_priv) Loading Loading @@ -4172,6 +4211,7 @@ static void cnss_pci_dump_registers(struct cnss_pci_data *pci_priv) return; mhi_debug_reg_dump(pci_priv->mhi_ctrl); cnss_pci_soc_scratch_reg_dump(pci_priv); cnss_pci_dump_ce_reg(pci_priv, CNSS_CE_COMMON); cnss_pci_dump_ce_reg(pci_priv, CNSS_CE_09); cnss_pci_dump_ce_reg(pci_priv, CNSS_CE_10); Loading Loading @@ -4615,6 +4655,7 @@ static void cnss_dev_rddm_timeout_hdlr(struct timer_list *t) cnss_pr_err("Unable to collect ramdumps due to abrupt reset\n"); mhi_debug_reg_dump(mhi_ctrl); cnss_pci_soc_scratch_reg_dump(pci_priv); cnss_schedule_recovery(&pci_priv->pci_dev->dev, CNSS_REASON_TIMEOUT); } Loading drivers/net/wireless/cnss2/reg.h +5 −0 Original line number Diff line number Diff line Loading @@ -287,4 +287,9 @@ #define SRAM_START 0x01400000 #define SRAM_END 0x01800000 /* PCIE SOC scratch registers, address same for QCA6390 & QCA6490*/ #define PCIE_SCRATCH_0_SOC_PCIE_REG 0x1E04040 #define PCIE_SCRATCH_1_SOC_PCIE_REG 0x1E04044 #define PCIE_SCRATCH_2_SOC_PCIE_REG 0x1E0405C #endif Loading
drivers/net/wireless/cnss2/pci.c +41 −0 Original line number Diff line number Diff line Loading @@ -130,6 +130,13 @@ static struct cnss_pci_reg qdss_csr[] = { { NULL }, }; static struct cnss_pci_reg pci_scratch[] = { { "PCIE_SCRATCH_0", PCIE_SCRATCH_0_SOC_PCIE_REG }, { "PCIE_SCRATCH_1", PCIE_SCRATCH_1_SOC_PCIE_REG }, { "PCIE_SCRATCH_2", PCIE_SCRATCH_2_SOC_PCIE_REG }, { NULL }, }; static struct cnss_misc_reg wcss_reg_access_seq[] = { {0, QCA6390_GCC_DEBUG_CLK_CTL, 0}, {1, QCA6390_GCC_DEBUG_CLK_CTL, 0x802}, Loading Loading @@ -722,6 +729,35 @@ static int cnss_set_pci_link(struct cnss_pci_data *pci_priv, bool link_up) return ret; } static void cnss_pci_soc_scratch_reg_dump(struct cnss_pci_data *pci_priv) { u32 reg_offset, val; int i; switch (pci_priv->device_id) { case QCA6490_DEVICE_ID: break; default: return; } if (in_interrupt() || irqs_disabled()) return; if (cnss_pci_check_link_status(pci_priv)) return; cnss_pr_dbg("Start to dump SOC Scratch registers\n"); for (i = 0; pci_scratch[i].name; i++) { reg_offset = pci_scratch[i].offset; if (cnss_pci_reg_read(pci_priv, reg_offset, &val)) return; cnss_pr_dbg("PCIE_SOC_REG_%s = 0x%x\n", pci_scratch[i].name, val); } } int cnss_suspend_pci_link(struct cnss_pci_data *pci_priv) { int ret = 0; Loading Loading @@ -841,6 +877,7 @@ int cnss_pci_recover_link_down(struct cnss_pci_data *pci_priv) jiffies + msecs_to_jiffies(DEV_RDDM_TIMEOUT)); mhi_debug_reg_dump(pci_priv->mhi_ctrl); cnss_pci_soc_scratch_reg_dump(pci_priv); return 0; } Loading Loading @@ -1758,6 +1795,7 @@ static void cnss_pci_dump_misc_reg(struct cnss_pci_data *pci_priv) return; mhi_debug_reg_dump(pci_priv->mhi_ctrl); cnss_pci_soc_scratch_reg_dump(pci_priv); cnss_pci_misc_reg_dump(pci_priv, pci_priv->wcss_reg, pci_priv->wcss_reg_size, "wcss"); cnss_pci_misc_reg_dump(pci_priv, pci_priv->pcie_reg, Loading @@ -1775,6 +1813,7 @@ static void cnss_pci_dump_mhi_reg(struct cnss_pci_data *pci_priv) return; mhi_debug_reg_dump(pci_priv->mhi_ctrl); cnss_pci_soc_scratch_reg_dump(pci_priv); } static void cnss_pci_dump_shadow_reg(struct cnss_pci_data *pci_priv) Loading Loading @@ -4172,6 +4211,7 @@ static void cnss_pci_dump_registers(struct cnss_pci_data *pci_priv) return; mhi_debug_reg_dump(pci_priv->mhi_ctrl); cnss_pci_soc_scratch_reg_dump(pci_priv); cnss_pci_dump_ce_reg(pci_priv, CNSS_CE_COMMON); cnss_pci_dump_ce_reg(pci_priv, CNSS_CE_09); cnss_pci_dump_ce_reg(pci_priv, CNSS_CE_10); Loading Loading @@ -4615,6 +4655,7 @@ static void cnss_dev_rddm_timeout_hdlr(struct timer_list *t) cnss_pr_err("Unable to collect ramdumps due to abrupt reset\n"); mhi_debug_reg_dump(mhi_ctrl); cnss_pci_soc_scratch_reg_dump(pci_priv); cnss_schedule_recovery(&pci_priv->pci_dev->dev, CNSS_REASON_TIMEOUT); } Loading
drivers/net/wireless/cnss2/reg.h +5 −0 Original line number Diff line number Diff line Loading @@ -287,4 +287,9 @@ #define SRAM_START 0x01400000 #define SRAM_END 0x01800000 /* PCIE SOC scratch registers, address same for QCA6390 & QCA6490*/ #define PCIE_SCRATCH_0_SOC_PCIE_REG 0x1E04040 #define PCIE_SCRATCH_1_SOC_PCIE_REG 0x1E04044 #define PCIE_SCRATCH_2_SOC_PCIE_REG 0x1E0405C #endif