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Commit 43f1fa49 authored by qctecmdr Service's avatar qctecmdr Service Committed by Gerrit - the friendly Code Review server
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Merge "drivers: llcc: Write to sub-cache register based on version"

parents 59fb0fc3 bc71cf75

Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt

+2 −2
Original line number Diff line number Diff line
@@ -11,7 +11,7 @@ Properties: 
- compatible:

	Usage: required

	Value type: <string>

	Definition: must be "qcom,kona-llcc" or "qcom,lito-llcc"

	Definition: must be "qcom,llcc-v1" or "qcom,llcc-v2"



- reg:

	Usage: required
@@ -41,7 +41,7 @@ Properties: 
Example:



	cache-controller@9200000 {

		compatible = "qcom,kona-llcc";

		compatible = "qcom,llcc-v2";

		reg = <0x9200000 0x200000> <0x9600000 0x50000>;

		reg-names = "llcc_base", "llcc_broadcast_base";

		interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;

arch/arm64/boot/dts/qcom/kona.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -722,7 +722,7 @@ 
	};



	cache-controller@9200000 {

		compatible = "qcom,kona-llcc";

		compatible = "qcom,llcc-v2";

		reg = <0x9200000 0x1d0000> , <0x9600000 0x50000>;

		reg-names = "llcc_base", "llcc_broadcast_base";

		cap-based-alloc-and-pwr-collapse;

drivers/soc/qcom/llcc-kona.c

+1 −1
Original line number Diff line number Diff line
@@ -76,7 +76,7 @@ static int kona_qcom_llcc_probe(struct platform_device *pdev) 
}



static const struct of_device_id kona_qcom_llcc_of_match[] = {

	{ .compatible = "qcom,kona-llcc", },

	{ .compatible = "qcom,llcc-v2", },

	{ },

};

drivers/soc/qcom/llcc-slice.c

+37 −3
Original line number Diff line number Diff line
@@ -42,6 +42,10 @@ 
#define LLCC_TRP_ATTR0_CFGn(n)        (0x21000 + SZ_8 * n)

#define LLCC_TRP_ATTR1_CFGn(n)        (0x21004 + SZ_8 * n)



#define LLCC_TRP_C_AS_NC	      0x21F90

#define LLCC_TRP_NC_AS_C	      0x21F94

#define LLCC_FEAC_C_AS_NC	      0x35030

#define LLCC_FEAC_NC_AS_C	      0x35034

#define LLCC_TRP_WRSC_EN              0x21F20

#define LLCC_WRSC_SCID_EN(n)          BIT(n)
@@ -232,15 +236,44 @@ static int qcom_llcc_cfg_program(struct platform_device *pdev) 
	u32 sz;

	u32 pcb = 0;

	u32 cad = 0;

	u32 wren = 0;

	int ret = 0;

	const struct llcc_slice_config *llcc_table;

	struct llcc_slice_desc desc;

	bool cap_based_alloc_and_pwr_collapse =

		drv_data->cap_based_alloc_and_pwr_collapse;

	uint32_t mask = ~0;

	int v2_ver = of_device_is_compatible(pdev->dev.of_node,

							 "qcom,llcc-v2");



	sz = drv_data->cfg_size;

	llcc_table = drv_data->cfg;



	/* Disable the Cache as Non-Cache override and enable

	 * the Non-Cache as Cache override

	 */

	if (v2_ver) {

		ret  = regmap_write(drv_data->bcast_regmap,

						 LLCC_TRP_C_AS_NC, 0);

		if (ret)

			return ret;



		ret = regmap_write(drv_data->bcast_regmap,

						 LLCC_TRP_NC_AS_C, mask);

		if (ret)

			return ret;

	} else {

		ret  = regmap_write(drv_data->bcast_regmap,

						 LLCC_FEAC_C_AS_NC, 0);

		if (ret)

			return ret;



		ret = regmap_write(drv_data->bcast_regmap,

						 LLCC_FEAC_NC_AS_C, mask);

		if (ret)

			return ret;

	}



	for (i = 0; i < sz; i++) {

		attr1_cfg = LLCC_TRP_ATTR1_CFGn(llcc_table[i].slice_id);

		attr0_cfg = LLCC_TRP_ATTR0_CFGn(llcc_table[i].slice_id);
@@ -277,10 +310,11 @@ static int qcom_llcc_cfg_program(struct platform_device *pdev) 
		if (ret)

			return ret;



		if (llcc_table[i].write_scid_en) {

		if (v2_ver) {

			wren |= llcc_table[i].write_scid_en <<

						llcc_table[i].slice_id;

			ret = regmap_write(drv_data->bcast_regmap,

				LLCC_TRP_WRSC_EN,

				LLCC_WRSC_SCID_EN(llcc_table[i].slice_id));

				LLCC_TRP_WRSC_EN, wren);

			if (ret)

				return ret;

		}