Merge "ARM: dts: msm: Add GPU properties for Khaje" (43ebf455) · Commits · e / devices / android_kernel_oneplus_sm7250

qcom/khaje.dtsi

+366 −0

Original line number	Diff line number	Diff line
		@@ -3001,6 +3001,372 @@ tpdm_turing_llm: tpdm@8861000 {
		#include "khaje-sde-pll.dtsi"
		#include "khaje-sde.dtsi"

		&soc {
		/delete-node/ gpu_bw_tbl;
		/delete-node/ gpubw;
		/delete-node/ gpu_opp_table;

		gpu_bw_tbl: gpu-bw-tbl {
		compatible = "operating-points-v2";
		BW_OPP_ENTRY( 0, 8); /* 0 MB/s */
		BW_OPP_ENTRY( 200, 8); /* 1525 MB/s */
		BW_OPP_ENTRY( 547, 8); /* 4173 MB/s */
		BW_OPP_ENTRY( 768, 8); /* 5859 MB/s */
		BW_OPP_ENTRY(1017, 8); /* 7759 MB/s */
		BW_OPP_ENTRY(1555, 8); /11863 MB/s /
		BW_OPP_ENTRY(1804, 8); /13763 MB/s /
		BW_OPP_ENTRY(2092, 8); /15960 MB/s /
		};

		gpubw: qcom,gpubw {
		compatible = "qcom,devbw";
		governor = "bw_vbif";
		qcom,src-dst-ports = <26 512>;
		operating-points-v2 = <&gpu_bw_tbl>;
		};

		gpu_opp_table: gpu-opp-table {
		compatible = "operating-points-v2";

		opp-1115000000 {
		opp-hz = /bits/ 64 <1115000000>;
		opp-microvolt = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
		};

		opp-1100000000 {
		opp-hz = /bits/ 64 <1100000000>;
		opp-microvolt = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
		};

		opp-1025000000 {
		opp-hz = /bits/ 64 <1025000000>;
		opp-microvolt = <RPMH_REGULATOR_LEVEL_TURBO>;
		};

		opp-980000000 {
		opp-hz = /bits/ 64 <980000000>;
		opp-microvolt = <RPMH_REGULATOR_LEVEL_TURBO>;
		};

		opp-820000000 {
		opp-hz = /bits/ 64 <820000000>;
		opp-microvolt = <RPMH_REGULATOR_LEVEL_NOM_L1>;
		};

		opp-785000000 {
		opp-hz = /bits/ 64 <785000000>;
		opp-microvolt = <RPMH_REGULATOR_LEVEL_NOM>;
		};

		opp-600000000 {
		opp-hz = /bits/ 64 <600000000>;
		opp-microvolt = <RPMH_REGULATOR_LEVEL_SVS_L1>;
		};

		opp-465000000 {
		opp-hz = /bits/ 64 <465000000>;
		opp-microvolt = <RPMH_REGULATOR_LEVEL_SVS>;
		};

		opp-320000000 {
		opp-hz = /bits/ 64 <320000000>;
		opp-microvolt = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
		};
		};
		};

		&msm_gpu {
		qcom,chipid = <0x06010001>;
		qcom,msm-bus,num-cases = <8>;
		qcom,msm-bus,vectors-KBps =
		<26 512 0 0>,
		<26 512 0 1600000>, /* 1 bus=200 (LOW SVS) */
		<26 512 0 4376000>, /* 2 bus=547 (LOW SVS) */
		<26 512 0 6144000>, /* 3 bus=768 (SVS) */
		<26 512 0 8136000>, /* 4 bus=1017 (SVS_L1) */
		<26 512 0 12440000>, /* 5 bus=1555 (NOM) */
		<26 512 0 14432000>, /* 6 bus=1804 (TURBO) */
		<26 512 0 16736000>; /* 7 bus=2092 (TURBO_L1) */

		/delete-node/ qcom,gpu-pwrlevel-bins;
		/*
		* Speed-bin zero is default speed bin.
		* For rest of the speed bins, speed-bin value
		* is calculated as FMAX/4.8 MHz round up to zero
		* decimal places plus two margin to account for
		* clock jitters.
		*/
		qcom,gpu-pwrlevel-bins {
		#address-cells = <1>;
		#size-cells = <0>;

		compatible = "qcom,gpu-pwrlevel-bins";

		qcom,gpu-pwrlevels-0 {
		#address-cells = <1>;
		#size-cells = <0>;

		qcom,speed-bin = <0>;

		qcom,initial-pwrlevel = <8>;
		qcom,ca-target-pwrlevel = <7>;

		/* TURBO_L1 */
		qcom,gpu-pwrlevel@0 {
		reg = <0>;
		qcom,gpu-freq = <111500000>;
		qcom,bus-freq = <7>;
		qcom,bus-min = <7>;
		qcom,bus-max = <7>;
		};

		/* TURBO_L1 */
		qcom,gpu-pwrlevel@1 {
		reg = <1>;
		qcom,gpu-freq = <110000000>;
		qcom,bus-freq = <7>;
		qcom,bus-min = <6>;
		qcom,bus-max = <7>;
		};

		/* TURBO */
		qcom,gpu-pwrlevel@2 {
		reg = <2>;
		qcom,gpu-freq = <1025000000>;
		qcom,bus-freq = <6>;
		qcom,bus-min = <6>;
		qcom,bus-max = <7>;
		};
		/* TURBO */
		qcom,gpu-pwrlevel@3 {
		reg = <3>;
		qcom,gpu-freq = <980000000>;
		qcom,bus-freq = <6>;
		qcom,bus-min = <5>;
		qcom,bus-max = <6>;
		};

		/* NOM_L1 */
		qcom,gpu-pwrlevel@4 {
		reg = <4>;
		qcom,gpu-freq = <820000000>;
		qcom,bus-freq = <5>;
		qcom,bus-min = <4>;
		qcom,bus-max = <6>;
		};

		/* NOM */
		qcom,gpu-pwrlevel@5 {
		reg = <5>;
		qcom,gpu-freq = <785000000>;
		qcom,bus-freq = <5>;
		qcom,bus-min = <4>;
		qcom,bus-max = <5>;
		};

		/* SVS_L1 */
		qcom,gpu-pwrlevel@6 {
		reg = <6>;
		qcom,gpu-freq = <600000000>;
		qcom,bus-freq = <4>;
		qcom,bus-min = <3>;
		qcom,bus-max = <5>;
		};

		/* SVS */
		qcom,gpu-pwrlevel@7 {
		reg = <7>;
		qcom,gpu-freq = <465000000>;
		qcom,bus-freq = <3>;
		qcom,bus-min = <2>;
		qcom,bus-max = <4>;
		};

		/* LOW SVS */
		qcom,gpu-pwrlevel@8 {
		reg = <8>;
		qcom,gpu-freq = <320000000>;
		qcom,bus-freq = <2>;
		qcom,bus-min = <1>;
		qcom,bus-max = <2>;
		};

		/* XO */
		qcom,gpu-pwrlevel@9 {
		reg = <9>;
		qcom,gpu-freq = <0>;
		qcom,bus-freq = <0>;
		qcom,bus-min = <0>;
		qcom,bus-max = <0>;
		};
		};

		qcom,gpu-pwrlevels-1 {
		#address-cells = <1>;
		#size-cells = <0>;

		qcom,speed-bin = <232>;

		qcom,initial-pwrlevel = <7>;
		qcom,ca-target-pwrlevel = <6>;

		/* TURBO_L1 */
		qcom,gpu-pwrlevel@0 {
		reg = <0>;
		qcom,gpu-freq = <110000000>;
		qcom,bus-freq = <7>;
		qcom,bus-min = <6>;
		qcom,bus-max = <7>;
		};

		/* TURBO */
		qcom,gpu-pwrlevel@1 {
		reg = <1>;
		qcom,gpu-freq = <1025000000>;
		qcom,bus-freq = <6>;
		qcom,bus-min = <6>;
		qcom,bus-max = <7>;
		};

		/* TURBO */
		qcom,gpu-pwrlevel@2 {
		reg = <2>;
		qcom,gpu-freq = <980000000>;
		qcom,bus-freq = <6>;
		qcom,bus-min = <5>;
		qcom,bus-max = <6>;
		};

		/* NOM_L1 */
		qcom,gpu-pwrlevel@3 {
		reg = <3>;
		qcom,gpu-freq = <820000000>;
		qcom,bus-freq = <5>;
		qcom,bus-min = <4>;
		qcom,bus-max = <6>;
		};

		/* NOM */
		qcom,gpu-pwrlevel@4 {
		reg = <4>;
		qcom,gpu-freq = <785000000>;
		qcom,bus-freq = <5>;
		qcom,bus-min = <4>;
		qcom,bus-max = <5>;
		};

		/* SVS_L1 */
		qcom,gpu-pwrlevel@5 {
		reg = <5>;
		qcom,gpu-freq = <600000000>;
		qcom,bus-freq = <4>;
		qcom,bus-min = <3>;
		qcom,bus-max = <5>;
		};

		/* SVS */
		qcom,gpu-pwrlevel@6 {
		reg = <6>;
		qcom,gpu-freq = <465000000>;
		qcom,bus-freq = <3>;
		qcom,bus-min = <2>;
		qcom,bus-max = <4>;
		};

		/* LOW SVS */
		qcom,gpu-pwrlevel@7 {
		reg = <7>;
		qcom,gpu-freq = <320000000>;
		qcom,bus-freq = <2>;
		qcom,bus-min = <1>;
		qcom,bus-max = <2>;
		};

		/* XO */
		qcom,gpu-pwrlevel@8 {
		reg = <8>;
		qcom,gpu-freq = <0>;
		qcom,bus-freq = <0>;
		qcom,bus-min = <0>;
		qcom,bus-max = <0>;
		};
		};

		qcom,gpu-pwrlevels-2 {
		#address-cells = <1>;
		#size-cells = <0>;

		qcom,speed-bin = <207>;

		qcom,initial-pwrlevel = <5>;
		qcom,ca-target-pwrlevel = <4>;

		/* TURBO */
		qcom,gpu-pwrlevel@0 {
		reg = <0>;
		qcom,gpu-freq = <980000000>;
		qcom,bus-freq = <6>;
		qcom,bus-min = <5>;
		qcom,bus-max = <6>;
		};

		/* NOM_L1 */
		qcom,gpu-pwrlevel@1 {
		reg = <1>;
		qcom,gpu-freq = <820000000>;
		qcom,bus-freq = <5>;
		qcom,bus-min = <4>;
		qcom,bus-max = <6>;
		};

		/* NOM */
		qcom,gpu-pwrlevel@2 {
		reg = <2>;
		qcom,gpu-freq = <785000000>;
		qcom,bus-freq = <5>;
		qcom,bus-min = <4>;
		qcom,bus-max = <5>;
		};

		/* SVS_L1 */
		qcom,gpu-pwrlevel@3 {
		reg = <3>;
		qcom,gpu-freq = <600000000>;
		qcom,bus-freq = <4>;
		qcom,bus-min = <3>;
		qcom,bus-max = <5>;
		};

		/* SVS */
		qcom,gpu-pwrlevel@4 {
		reg = <4>;
		qcom,gpu-freq = <465000000>;
		qcom,bus-freq = <3>;
		qcom,bus-min = <2>;
		qcom,bus-max = <4>;
		};

		/* LOW SVS */
		qcom,gpu-pwrlevel@5 {
		reg = <5>;
		qcom,gpu-freq = <320000000>;
		qcom,bus-freq = <2>;
		qcom,bus-min = <1>;
		qcom,bus-max = <2>;
		};

		/* XO */
		qcom,gpu-pwrlevel@6 {
		reg = <6>;
		qcom,gpu-freq = <0>;
		qcom,bus-freq = <0>;
		qcom,bus-min = <0>;
		qcom,bus-max = <0>;
		};
		};
		};
		};

		&qupv3_se1_i2c {
		status = "ok";
		#include "pm8008.dtsi"