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Commit 437ae6a1 authored by Stephen Boyd's avatar Stephen Boyd Committed by Mike Turquette
Browse files

clk: qcom: Fix mmcc-8974's PLL configurations 



We forgot to add the status bit for the PLLs and we were using
the wrong register and masks for configuration, leading to
unexpected PLL configurations. Fix this.

Fixes: d8b21201 (clk: qcom: Add support for MSM8974's multimedia clock controller (MMCC))
Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: default avatarMike Turquette <mturquette@linaro.org>
parent aa014149

drivers/clk/qcom/mmcc-msm8974.c

+8 −5
Original line number Diff line number Diff line
@@ -170,6 +170,7 @@ static struct clk_pll mmpll0 = { 
	.config_reg = 0x0014,

	.mode_reg = 0x0000,

	.status_reg = 0x001c,

	.status_bit = 17,

        .clkr.hw.init = &(struct clk_init_data){

                .name = "mmpll0",

                .parent_names = (const char *[]){ "xo" },
@@ -193,9 +194,10 @@ static struct clk_pll mmpll1 = { 
	.l_reg = 0x0044,

	.m_reg = 0x0048,

	.n_reg = 0x004c,

	.config_reg = 0x0054,

	.config_reg = 0x0050,

	.mode_reg = 0x0040,

	.status_reg = 0x005c,

	.status_bit = 17,

        .clkr.hw.init = &(struct clk_init_data){

                .name = "mmpll1",

                .parent_names = (const char *[]){ "xo" },
@@ -219,7 +221,7 @@ static struct clk_pll mmpll2 = { 
	.l_reg = 0x4104,

	.m_reg = 0x4108,

	.n_reg = 0x410c,

	.config_reg = 0x4114,

	.config_reg = 0x4110,

	.mode_reg = 0x4100,

	.status_reg = 0x411c,

        .clkr.hw.init = &(struct clk_init_data){
@@ -234,9 +236,10 @@ static struct clk_pll mmpll3 = { 
	.l_reg = 0x0084,

	.m_reg = 0x0088,

	.n_reg = 0x008c,

	.config_reg = 0x0094,

	.config_reg = 0x0090,

	.mode_reg = 0x0080,

	.status_reg = 0x009c,

	.status_bit = 17,

        .clkr.hw.init = &(struct clk_init_data){

                .name = "mmpll3",

                .parent_names = (const char *[]){ "xo" },
@@ -2319,7 +2322,7 @@ static const struct pll_config mmpll1_config = { 
	.vco_val = 0x0,

	.vco_mask = 0x3 << 20,

	.pre_div_val = 0x0,

	.pre_div_mask = 0x3 << 12,

	.pre_div_mask = 0x7 << 12,

	.post_div_val = 0x0,

	.post_div_mask = 0x3 << 8,

	.mn_ena_mask = BIT(24),
@@ -2333,7 +2336,7 @@ static struct pll_config mmpll3_config = { 
	.vco_val = 0x0,

	.vco_mask = 0x3 << 20,

	.pre_div_val = 0x0,

	.pre_div_mask = 0x3 << 12,

	.pre_div_mask = 0x7 << 12,

	.post_div_val = 0x0,

	.post_div_mask = 0x3 << 8,

	.mn_ena_mask = BIT(24),