Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 4359cf33 authored by Rahul Lakkireddy's avatar Rahul Lakkireddy Committed by David S. Miller
Browse files

cxgb4: collect TP dump 



Signed-off-by: default avatarRahul Lakkireddy <rahul.lakkireddy@chelsio.com>
Signed-off-by: default avatarGanesh Goudar <ganeshgr@chelsio.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 5ccf9d04

drivers/net/ethernet/chelsio/cxgb4/cudbg_entity.h

+72 −0
Original line number Diff line number Diff line
@@ -32,4 +32,76 @@ struct cudbg_mbox_log { 
	u32 hi[MBOX_LEN / 8];

	u32 lo[MBOX_LEN / 8];

};



struct ireg_field {

	u32 ireg_addr;

	u32 ireg_data;

	u32 ireg_local_offset;

	u32 ireg_offset_range;

};



struct ireg_buf {

	struct ireg_field tp_pio;

	u32 outbuf[32];

};



#define IREG_NUM_ELEM 4



static const u32 t6_tp_pio_array[][IREG_NUM_ELEM] = {

	{0x7e40, 0x7e44, 0x020, 28}, /* t6_tp_pio_regs_20_to_3b */

	{0x7e40, 0x7e44, 0x040, 10}, /* t6_tp_pio_regs_40_to_49 */

	{0x7e40, 0x7e44, 0x050, 10}, /* t6_tp_pio_regs_50_to_59 */

	{0x7e40, 0x7e44, 0x060, 14}, /* t6_tp_pio_regs_60_to_6d */

	{0x7e40, 0x7e44, 0x06F, 1}, /* t6_tp_pio_regs_6f */

	{0x7e40, 0x7e44, 0x070, 6}, /* t6_tp_pio_regs_70_to_75 */

	{0x7e40, 0x7e44, 0x130, 18}, /* t6_tp_pio_regs_130_to_141 */

	{0x7e40, 0x7e44, 0x145, 19}, /* t6_tp_pio_regs_145_to_157 */

	{0x7e40, 0x7e44, 0x160, 1}, /* t6_tp_pio_regs_160 */

	{0x7e40, 0x7e44, 0x230, 25}, /* t6_tp_pio_regs_230_to_248 */

	{0x7e40, 0x7e44, 0x24a, 3}, /* t6_tp_pio_regs_24c */

	{0x7e40, 0x7e44, 0x8C0, 1} /* t6_tp_pio_regs_8c0 */

};



static const u32 t5_tp_pio_array[][IREG_NUM_ELEM] = {

	{0x7e40, 0x7e44, 0x020, 28}, /* t5_tp_pio_regs_20_to_3b */

	{0x7e40, 0x7e44, 0x040, 19}, /* t5_tp_pio_regs_40_to_52 */

	{0x7e40, 0x7e44, 0x054, 2}, /* t5_tp_pio_regs_54_to_55 */

	{0x7e40, 0x7e44, 0x060, 13}, /* t5_tp_pio_regs_60_to_6c */

	{0x7e40, 0x7e44, 0x06F, 1}, /* t5_tp_pio_regs_6f */

	{0x7e40, 0x7e44, 0x120, 4}, /* t5_tp_pio_regs_120_to_123 */

	{0x7e40, 0x7e44, 0x12b, 2}, /* t5_tp_pio_regs_12b_to_12c */

	{0x7e40, 0x7e44, 0x12f, 21}, /* t5_tp_pio_regs_12f_to_143 */

	{0x7e40, 0x7e44, 0x145, 19}, /* t5_tp_pio_regs_145_to_157 */

	{0x7e40, 0x7e44, 0x230, 25}, /* t5_tp_pio_regs_230_to_248 */

	{0x7e40, 0x7e44, 0x8C0, 1} /* t5_tp_pio_regs_8c0 */

};



static const u32 t6_tp_tm_pio_array[][IREG_NUM_ELEM] = {

	{0x7e18, 0x7e1c, 0x0, 12}

};



static const u32 t5_tp_tm_pio_array[][IREG_NUM_ELEM] = {

	{0x7e18, 0x7e1c, 0x0, 12}

};



static const u32 t6_tp_mib_index_array[6][IREG_NUM_ELEM] = {

	{0x7e50, 0x7e54, 0x0, 13},

	{0x7e50, 0x7e54, 0x10, 6},

	{0x7e50, 0x7e54, 0x18, 21},

	{0x7e50, 0x7e54, 0x30, 32},

	{0x7e50, 0x7e54, 0x50, 22},

	{0x7e50, 0x7e54, 0x68, 12}

};



static const u32 t5_tp_mib_index_array[9][IREG_NUM_ELEM] = {

	{0x7e50, 0x7e54, 0x0, 13},

	{0x7e50, 0x7e54, 0x10, 6},

	{0x7e50, 0x7e54, 0x18, 8},

	{0x7e50, 0x7e54, 0x20, 13},

	{0x7e50, 0x7e54, 0x30, 16},

	{0x7e50, 0x7e54, 0x40, 16},

	{0x7e50, 0x7e54, 0x50, 16},

	{0x7e50, 0x7e54, 0x60, 6},

	{0x7e50, 0x7e54, 0x68, 4}

};

#endif /* __CUDBG_ENTITY_H__ */

drivers/net/ethernet/chelsio/cxgb4/cudbg_if.h

+1 −0
Original line number Diff line number Diff line
@@ -31,6 +31,7 @@ enum cudbg_dbg_entity_type { 
	CUDBG_DEV_LOG = 2,

	CUDBG_EDC0 = 18,

	CUDBG_EDC1 = 19,

	CUDBG_TP_INDIRECT = 36,

	CUDBG_MBOX_LOG = 66,

	CUDBG_MAX_ENTITY = 70,

};

drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c

+114 −0
Original line number Diff line number Diff line
@@ -253,6 +253,120 @@ int cudbg_collect_edc1_meminfo(struct cudbg_init *pdbg_init, 
					MEM_EDC1);

}



int cudbg_collect_tp_indirect(struct cudbg_init *pdbg_init,

			      struct cudbg_buffer *dbg_buff,

			      struct cudbg_error *cudbg_err)

{

	struct adapter *padap = pdbg_init->adap;

	struct cudbg_buffer temp_buff = { 0 };

	struct ireg_buf *ch_tp_pio;

	int i, rc, n = 0;

	u32 size;



	if (is_t5(padap->params.chip))

		n = sizeof(t5_tp_pio_array) +

		    sizeof(t5_tp_tm_pio_array) +

		    sizeof(t5_tp_mib_index_array);

	else

		n = sizeof(t6_tp_pio_array) +

		    sizeof(t6_tp_tm_pio_array) +

		    sizeof(t6_tp_mib_index_array);



	n = n / (IREG_NUM_ELEM * sizeof(u32));

	size = sizeof(struct ireg_buf) * n;

	rc = cudbg_get_buff(dbg_buff, size, &temp_buff);

	if (rc)

		return rc;



	ch_tp_pio = (struct ireg_buf *)temp_buff.data;



	/* TP_PIO */

	if (is_t5(padap->params.chip))

		n = sizeof(t5_tp_pio_array) / (IREG_NUM_ELEM * sizeof(u32));

	else if (is_t6(padap->params.chip))

		n = sizeof(t6_tp_pio_array) / (IREG_NUM_ELEM * sizeof(u32));



	for (i = 0; i < n; i++) {

		struct ireg_field *tp_pio = &ch_tp_pio->tp_pio;

		u32 *buff = ch_tp_pio->outbuf;



		if (is_t5(padap->params.chip)) {

			tp_pio->ireg_addr = t5_tp_pio_array[i][0];

			tp_pio->ireg_data = t5_tp_pio_array[i][1];

			tp_pio->ireg_local_offset = t5_tp_pio_array[i][2];

			tp_pio->ireg_offset_range = t5_tp_pio_array[i][3];

		} else if (is_t6(padap->params.chip)) {

			tp_pio->ireg_addr = t6_tp_pio_array[i][0];

			tp_pio->ireg_data = t6_tp_pio_array[i][1];

			tp_pio->ireg_local_offset = t6_tp_pio_array[i][2];

			tp_pio->ireg_offset_range = t6_tp_pio_array[i][3];

		}

		t4_tp_pio_read(padap, buff, tp_pio->ireg_offset_range,

			       tp_pio->ireg_local_offset, true);

		ch_tp_pio++;

	}



	/* TP_TM_PIO */

	if (is_t5(padap->params.chip))

		n = sizeof(t5_tp_tm_pio_array) / (IREG_NUM_ELEM * sizeof(u32));

	else if (is_t6(padap->params.chip))

		n = sizeof(t6_tp_tm_pio_array) / (IREG_NUM_ELEM * sizeof(u32));



	for (i = 0; i < n; i++) {

		struct ireg_field *tp_pio = &ch_tp_pio->tp_pio;

		u32 *buff = ch_tp_pio->outbuf;



		if (is_t5(padap->params.chip)) {

			tp_pio->ireg_addr = t5_tp_tm_pio_array[i][0];

			tp_pio->ireg_data = t5_tp_tm_pio_array[i][1];

			tp_pio->ireg_local_offset = t5_tp_tm_pio_array[i][2];

			tp_pio->ireg_offset_range = t5_tp_tm_pio_array[i][3];

		} else if (is_t6(padap->params.chip)) {

			tp_pio->ireg_addr = t6_tp_tm_pio_array[i][0];

			tp_pio->ireg_data = t6_tp_tm_pio_array[i][1];

			tp_pio->ireg_local_offset = t6_tp_tm_pio_array[i][2];

			tp_pio->ireg_offset_range = t6_tp_tm_pio_array[i][3];

		}

		t4_tp_tm_pio_read(padap, buff, tp_pio->ireg_offset_range,

				  tp_pio->ireg_local_offset, true);

		ch_tp_pio++;

	}



	/* TP_MIB_INDEX */

	if (is_t5(padap->params.chip))

		n = sizeof(t5_tp_mib_index_array) /

		    (IREG_NUM_ELEM * sizeof(u32));

	else if (is_t6(padap->params.chip))

		n = sizeof(t6_tp_mib_index_array) /

		    (IREG_NUM_ELEM * sizeof(u32));



	for (i = 0; i < n ; i++) {

		struct ireg_field *tp_pio = &ch_tp_pio->tp_pio;

		u32 *buff = ch_tp_pio->outbuf;



		if (is_t5(padap->params.chip)) {

			tp_pio->ireg_addr = t5_tp_mib_index_array[i][0];

			tp_pio->ireg_data = t5_tp_mib_index_array[i][1];

			tp_pio->ireg_local_offset =

				t5_tp_mib_index_array[i][2];

			tp_pio->ireg_offset_range =

				t5_tp_mib_index_array[i][3];

		} else if (is_t6(padap->params.chip)) {

			tp_pio->ireg_addr = t6_tp_mib_index_array[i][0];

			tp_pio->ireg_data = t6_tp_mib_index_array[i][1];

			tp_pio->ireg_local_offset =

				t6_tp_mib_index_array[i][2];

			tp_pio->ireg_offset_range =

				t6_tp_mib_index_array[i][3];

		}

		t4_tp_mib_read(padap, buff, tp_pio->ireg_offset_range,

			       tp_pio->ireg_local_offset, true);

		ch_tp_pio++;

	}

	cudbg_write_and_release_buff(&temp_buff, dbg_buff);

	return rc;

}



int cudbg_collect_mbox_log(struct cudbg_init *pdbg_init,

			   struct cudbg_buffer *dbg_buff,

			   struct cudbg_error *cudbg_err)

drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.h

+3 −0
Original line number Diff line number Diff line
@@ -30,6 +30,9 @@ int cudbg_collect_edc0_meminfo(struct cudbg_init *pdbg_init, 
int cudbg_collect_edc1_meminfo(struct cudbg_init *pdbg_init,

			       struct cudbg_buffer *dbg_buff,

			       struct cudbg_error *cudbg_err);

int cudbg_collect_tp_indirect(struct cudbg_init *pdbg_init,

			      struct cudbg_buffer *dbg_buff,

			      struct cudbg_error *cudbg_err);

int cudbg_collect_mbox_log(struct cudbg_init *pdbg_init,

			   struct cudbg_buffer *dbg_buff,

			   struct cudbg_error *cudbg_err);

drivers/net/ethernet/chelsio/cxgb4/cxgb4.h

+2 −0
Original line number Diff line number Diff line
@@ -1634,6 +1634,8 @@ int t4_set_vf_mac_acl(struct adapter *adapter, unsigned int vf, 
		      unsigned int naddr, u8 *addr);

void t4_tp_pio_read(struct adapter *adap, u32 *buff, u32 nregs,

		    u32 start_index, bool sleep_ok);

void t4_tp_tm_pio_read(struct adapter *adap, u32 *buff, u32 nregs,

		       u32 start_index, bool sleep_ok);

void t4_tp_mib_read(struct adapter *adap, u32 *buff, u32 nregs,

		    u32 start_index, bool sleep_ok);