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Commit 4349c429 authored by Stefan Agner's avatar Stefan Agner Committed by Shawn Guo
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ARM: imx: clk-vf610: fix FlexCAN clock gating 



Extend the clock control for FlexCAN with the second gate which
enable the clocks in the Clock Divider (CCM_CSCDR2) register too.

Signed-off-by: default avatarStefan Agner <stefan@agner.ch>
Signed-off-by: default avatarShawn Guo <shawn.guo@freescale.com>
parent fd4959d8

arch/arm/mach-imx/clk-vf610.c

+4 −2
Original line number Diff line number Diff line
@@ -295,8 +295,10 @@ static void __init vf610_clocks_init(struct device_node *ccm_node) 


	clk[VF610_CLK_ASRC] = imx_clk_gate2("asrc", "ipg_bus", CCM_CCGR4, CCM_CCGRx_CGn(1));



	clk[VF610_CLK_FLEXCAN0] = imx_clk_gate2("flexcan0", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(0));

	clk[VF610_CLK_FLEXCAN1] = imx_clk_gate2("flexcan1", "ipg_bus", CCM_CCGR9, CCM_CCGRx_CGn(4));

	clk[VF610_CLK_FLEXCAN0_EN] = imx_clk_gate("flexcan0_en", "ipg_bus", CCM_CSCDR2, 11);

	clk[VF610_CLK_FLEXCAN0] = imx_clk_gate2("flexcan0", "flexcan0_en", CCM_CCGR0, CCM_CCGRx_CGn(0));

	clk[VF610_CLK_FLEXCAN1_EN] = imx_clk_gate("flexcan1_en", "ipg_bus", CCM_CSCDR2, 12);

	clk[VF610_CLK_FLEXCAN1] = imx_clk_gate2("flexcan1", "flexcan1_en", CCM_CCGR9, CCM_CCGRx_CGn(4));



	clk[VF610_CLK_DMAMUX0] = imx_clk_gate2("dmamux0", "platform_bus", CCM_CCGR0, CCM_CCGRx_CGn(4));

	clk[VF610_CLK_DMAMUX1] = imx_clk_gate2("dmamux1", "platform_bus", CCM_CCGR0, CCM_CCGRx_CGn(5));

include/dt-bindings/clock/vf610-clock.h

+3 −1
Original line number Diff line number Diff line
@@ -164,6 +164,8 @@ 
#define VF610_CLK_DMAMUX1		151

#define VF610_CLK_DMAMUX2		152

#define VF610_CLK_DMAMUX3		153

#define VF610_CLK_END			154

#define VF610_CLK_FLEXCAN0_EN		154

#define VF610_CLK_FLEXCAN1_EN		155

#define VF610_CLK_END			156



#endif /* __DT_BINDINGS_CLOCK_VF610_H */