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Commit 4283908e authored by Daniel Vetter's avatar Daniel Vetter
Browse files

drm/i915: Implement WaDisableHiZPlanesWhenMSAAEnabled 



Quoting from Bspec, 3D_CHICKEN1, bit 10

This bit needs to be set always to "1", Project: DevSNB "

Reviewed-by: default avatarRodrigo Vivi <rodrigo.vivi@gmail.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent f20e0b08

drivers/gpu/drm/i915/i915_reg.h

+1 −0
Original line number Diff line number Diff line
@@ -517,6 +517,7 @@ 
 * the enables for writing to the corresponding low bit.

 */

#define _3D_CHICKEN	0x02084

#define  _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB	(1 << 10)

#define _3D_CHICKEN2	0x0208c

/* Disables pipelining of read flushes past the SF-WIZ interface.

 * Required on all Ironlake steppings according to the B-Spec, but the

drivers/gpu/drm/i915/intel_pm.c

+4 −0
Original line number Diff line number Diff line
@@ -3592,6 +3592,10 @@ static void gen6_init_clock_gating(struct drm_device *dev) 
		   I915_READ(ILK_DISPLAY_CHICKEN2) |

		   ILK_ELPIN_409_SELECT);



	/* WaDisableHiZPlanesWhenMSAAEnabled */

	I915_WRITE(_3D_CHICKEN,

		   _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));



	I915_WRITE(WM3_LP_ILK, 0);

	I915_WRITE(WM2_LP_ILK, 0);

	I915_WRITE(WM1_LP_ILK, 0);