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Commit 422c3107 authored by Yisen.Zhuang\(Zhuangyuzeng\)'s avatar Yisen.Zhuang\(Zhuangyuzeng\) Committed by David S. Miller
Browse files

net: hns: add attribute reset-field-offset for dsaf node 



Add the subctrl reset offset for dsaf, this property is used to reset
xge/ge ports for different dsaf. If this attribute is not present,
default value 0 will be used.

Signed-off-by: default avatarDaode Huang <huangdaode@hisilicon.com>
Signed-off-by: default avatarYisen Zhuang <yisen.zhuang@huawei.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 406adee9

drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c

+8 −0
Original line number Diff line number Diff line
@@ -36,6 +36,7 @@ int hns_dsaf_get_cfg(struct dsaf_device *dsaf_dev) 
	int ret, i;

	u32 desc_num;

	u32 buf_size;

	u32 reset_offset = 0;

	const char *mode_str;

	struct device_node *np = dsaf_dev->dev->of_node;
@@ -119,6 +120,13 @@ int hns_dsaf_get_cfg(struct dsaf_device *dsaf_dev) 
	}

	dsaf_dev->desc_num = desc_num;



	ret = of_property_read_u32(np, "reset-field-offset", &reset_offset);

	if (ret < 0) {

		dev_dbg(dsaf_dev->dev,

			"get reset-field-offset fail, ret=%d!\r\n", ret);

	}

	dsaf_dev->reset_offset = reset_offset;



	ret = of_property_read_u32(np, "buf-size", &buf_size);

	if (ret < 0) {

		dev_err(dsaf_dev->dev,

drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.h

+1 −0
Original line number Diff line number Diff line
@@ -281,6 +281,7 @@ struct dsaf_device { 


	u32 desc_num; /*  desc num per queue*/

	u32 buf_size; /*  ring buffer size */

	u32 reset_offset; /* reset field offset in sub sysctrl */

	int buf_size_type; /* ring buffer size-type */

	enum dsaf_mode dsaf_mode;	 /* dsaf mode  */

	enum hal_dsaf_mode dsaf_en;

drivers/net/ethernet/hisilicon/hns/hns_dsaf_misc.c

+28 −12
Original line number Diff line number Diff line
@@ -110,7 +110,11 @@ void hns_dsaf_xge_srst_by_port(struct dsaf_device *dsaf_dev, u32 port, u32 val) 
		return;



	reg_val |= RESET_REQ_OR_DREQ;



	if (!HNS_DSAF_IS_DEBUG(dsaf_dev))

		reg_val |= 0x2082082 << port;

	else

		reg_val |= 0x2082082 << (dsaf_dev->reset_offset + 6);



	if (val == 0)

		reg_addr = DSAF_SUB_SC_XGE_RESET_REQ_REG;
@@ -129,7 +133,11 @@ void hns_dsaf_xge_core_srst_by_port(struct dsaf_device *dsaf_dev, 
	if (port >= DSAF_XGE_NUM)

		return;



	if (!HNS_DSAF_IS_DEBUG(dsaf_dev))

		reg_val |= XGMAC_TRX_CORE_SRST_M << port;

	else

		reg_val |= XGMAC_TRX_CORE_SRST_M <<

			(dsaf_dev->reset_offset + 6);



	if (val == 0)

		reg_addr = DSAF_SUB_SC_XGE_RESET_REQ_REG;
@@ -173,8 +181,8 @@ void hns_dsaf_ge_srst_by_port(struct dsaf_device *dsaf_dev, u32 port, u32 val) 
				       reg_val_1);

		}

	} else {

		reg_val_1 = 0x15540 << (port - 6);

		reg_val_2 = 0x100 << (port - 6);

		reg_val_1 = 0x15540 << dsaf_dev->reset_offset;

		reg_val_2 = 0x100 << dsaf_dev->reset_offset;



		if (val == 0) {

			dsaf_write_reg(dsaf_dev->sc_base,
@@ -201,7 +209,11 @@ void hns_ppe_srst_by_port(struct dsaf_device *dsaf_dev, u32 port, u32 val) 
	u32 reg_val = 0;

	u32 reg_addr;



	if (!HNS_DSAF_IS_DEBUG(dsaf_dev))

		reg_val |= RESET_REQ_OR_DREQ << port;

	else

		reg_val |= RESET_REQ_OR_DREQ <<

			(dsaf_dev->reset_offset + 6);



	if (val == 0)

		reg_addr = DSAF_SUB_SC_PPE_RESET_REQ_REG;
@@ -213,7 +225,6 @@ void hns_ppe_srst_by_port(struct dsaf_device *dsaf_dev, u32 port, u32 val) 


void hns_ppe_com_srst(struct ppe_common_cb *ppe_common, u32 val)

{

	int comm_index = ppe_common->comm_index;

	struct dsaf_device *dsaf_dev = ppe_common->dsaf_dev;

	u32 reg_val;

	u32 reg_addr;
@@ -226,7 +237,7 @@ void hns_ppe_com_srst(struct ppe_common_cb *ppe_common, u32 val) 
			reg_addr = DSAF_SUB_SC_RCB_PPE_COM_RESET_DREQ_REG;



	} else {

		reg_val = 0x100 << (comm_index - 1);

		reg_val = 0x100 << dsaf_dev->reset_offset;



		if (val == 0)

			reg_addr = DSAF_SUB_SC_PPE_RESET_REQ_REG;
@@ -247,14 +258,16 @@ phy_interface_t hns_mac_get_phy_if(struct hns_mac_cb *mac_cb) 
	u32 mode;

	u32 reg;

	u32 shift;

	u32 phy_offset;

	bool is_ver1 = AE_IS_VER1(mac_cb->dsaf_dev->dsaf_ver);

	void __iomem *sys_ctl_vaddr = mac_cb->sys_ctl_vaddr;

	int mac_id = mac_cb->mac_id;

	phy_interface_t phy_if = PHY_INTERFACE_MODE_NA;



	if (is_ver1 && (mac_id >= 6 && mac_id <= 7)) {

	if (is_ver1 && HNS_DSAF_IS_DEBUG(mac_cb->dsaf_dev)) {

		phy_if = PHY_INTERFACE_MODE_SGMII;

	} else if (mac_id >= 0 && mac_id <= 3) {

	} else if (mac_id >= 0 && mac_id <= 3 &&

		   !HNS_DSAF_IS_DEBUG(mac_cb->dsaf_dev)) {

		reg = is_ver1 ? HNS_MAC_HILINK4_REG : HNS_MAC_HILINK4V2_REG;

		mode = dsaf_read_reg(sys_ctl_vaddr, reg);

		/* mac_id 0, 1, 2, 3 ---> hilink4 lane 0, 1, 2, 3 */
@@ -263,11 +276,14 @@ phy_interface_t hns_mac_get_phy_if(struct hns_mac_cb *mac_cb) 
			phy_if = PHY_INTERFACE_MODE_XGMII;

		else

			phy_if = PHY_INTERFACE_MODE_SGMII;

	} else if (mac_id >= 4 && mac_id <= 7) {

	} else {

		reg = is_ver1 ? HNS_MAC_HILINK3_REG : HNS_MAC_HILINK3V2_REG;

		mode = dsaf_read_reg(sys_ctl_vaddr, reg);

		/* mac_id 4, 5, 6, 7 ---> hilink3 lane 2, 3, 0, 1 */

		shift = is_ver1 ? 0 : mac_id <= 5 ? mac_id - 2 : mac_id - 6;

		/* mac_id 4, 5,---> hilink3 lane 2, 3

		 * debug port 0(6), 1(7) ---> hilink3 lane 0, 1

		 */

		phy_offset = mac_cb->dsaf_dev->reset_offset - 1;

		shift = is_ver1 ? 0 : mac_id >= 4 ? mac_id - 2 : phy_offset;

		if (dsaf_get_bit(mode, shift))

			phy_if = PHY_INTERFACE_MODE_XGMII;

		else