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Commit 41d5ffeb authored by Nobuhiro Iwamatsu's avatar Nobuhiro Iwamatsu Committed by David S. Miller
Browse files

sh_eth: remove #ifdef around EDSR and GECMR bit definitions 



Remove #ifdef around 'enum EDSR_BIT' and 'enum GECMR_BIT', replacing it with the
comments on which SoCs these registers exist.

SH7757 also has EDSR, so add a comment about it to 'enum EDSR_BIT'.

Signed-off-by: default avatarNobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
[Sergei: folded in the former patch #2, updated the changelog, reworded the
subject, changing the prefix.]
Signed-off-by: default avatarSergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 143554ac

drivers/net/ethernet/renesas/sh_eth.h

+2 −5
Original line number Original line Diff line number Diff line
@@ -166,19 +166,16 @@ enum { 
/*

/*

 * Register's bits

 * Register's bits

 */

 */

#if defined(CONFIG_CPU_SUBTYPE_SH7734) || defined(CONFIG_CPU_SUBTYPE_SH7763) ||\

/* EDSR : sh7734, sh7757, sh7763, and r8a7740 only */

    defined(CONFIG_ARCH_R8A7740)

/* EDSR */

enum EDSR_BIT {

enum EDSR_BIT {

	EDSR_ENT = 0x01, EDSR_ENR = 0x02,

	EDSR_ENT = 0x01, EDSR_ENR = 0x02,

};

};

#define EDSR_ENALL (EDSR_ENT|EDSR_ENR)

#define EDSR_ENALL (EDSR_ENT|EDSR_ENR)





/* GECMR */

/* GECMR : sh7734, sh7763 and r8a7740 only */

enum GECMR_BIT {

enum GECMR_BIT {

	GECMR_10 = 0x0, GECMR_100 = 0x04, GECMR_1000 = 0x01,

	GECMR_10 = 0x0, GECMR_100 = 0x04, GECMR_1000 = 0x01,

};

};

#endif





/* EDMR */

/* EDMR */

enum DMAC_M_BIT {

enum DMAC_M_BIT {