staging: brcm80211: reformat long lines in brcmsmac to 80 columns (419ad34e) · Commits · e / devices / android_kernel_oneplus_sm7250

drivers/staging/brcm80211/brcmsmac/aiutils.c

+123 −68

Original line number	Original line	Diff line number	Diff line
	@@ -28,48 +28,68 @@
	#include "aiutils.h"		#include "aiutils.h"

	/* slow_clk_ctl */		/* slow_clk_ctl */
	#define SCC_SS_MASK 0x00000007 /* slow clock source mask */		/* slow clock source mask */
	#define SCC_SS_LPO 0x00000000 /* source of slow clock is LPO */		#define SCC_SS_MASK 0x00000007
	#define SCC_SS_XTAL 0x00000001 /* source of slow clock is crystal */		/* source of slow clock is LPO */
	#define SCC_SS_PCI 0x00000002 /* source of slow clock is PCI */		#define SCC_SS_LPO 0x00000000
	#define SCC_LF 0x00000200 /* LPOFreqSel, 1: 160Khz, 0: 32KHz */		/* source of slow clock is crystal */
	#define SCC_LP 0x00000400 /* LPOPowerDown, 1: LPO is disabled,		#define SCC_SS_XTAL 0x00000001
	* 0: LPO is enabled		/* source of slow clock is PCI */
			#define SCC_SS_PCI 0x00000002
			/* LPOFreqSel, 1: 160Khz, 0: 32KHz */
			#define SCC_LF 0x00000200
			/* LPOPowerDown, 1: LPO is disabled, 0: LPO is enabled */
			#define SCC_LP 0x00000400
			/* ForceSlowClk, 1: sb/cores running on slow clock, 0: power logic control */
			#define SCC_FS 0x00000800
			/* IgnorePllOffReq, 1/0:
			* power logic ignores/honors PLL clock disable requests from core
	*/		*/
	#define SCC_FS 0x00000800 /* ForceSlowClk, 1: sb/cores running on slow clock,		#define SCC_IP 0x00001000
	* 0: power logic control		/* XtalControlEn, 1/0:
			* power logic does/doesn't disable crystal when appropriate
	*/		*/
	#define SCC_IP 0x00001000 /* IgnorePllOffReq, 1/0: power logic ignores/honors		#define SCC_XC 0x00002000
	* PLL clock disable requests from core		/* XtalPU (RO), 1/0: crystal running/disabled */
	*/		#define SCC_XP 0x00004000
	#define SCC_XC 0x00002000 /* XtalControlEn, 1/0: power logic does/doesn't		/* ClockDivider (SlowClk = 1/(4+divisor)) */
	* disable crystal when appropriate		#define SCC_CD_MASK 0xffff0000
	*/
	#define SCC_XP 0x00004000 /* XtalPU (RO), 1/0: crystal running/disabled */
	#define SCC_CD_MASK 0xffff0000 /* ClockDivider (SlowClk = 1/(4+divisor)) */
	#define SCC_CD_SHIFT 16		#define SCC_CD_SHIFT 16

	/* system_clk_ctl */		/* system_clk_ctl */
	#define SYCC_IE 0x00000001 /* ILPen: Enable Idle Low Power */		/* ILPen: Enable Idle Low Power */
	#define SYCC_AE 0x00000002 /* ALPen: Enable Active Low Power */		#define SYCC_IE 0x00000001
	#define SYCC_FP 0x00000004 /* ForcePLLOn */		/* ALPen: Enable Active Low Power */
	#define SYCC_AR 0x00000008 /* Force ALP (or HT if ALPen is not set */		#define SYCC_AE 0x00000002
	#define SYCC_HR 0x00000010 /* Force HT */		/* ForcePLLOn */
	#define SYCC_CD_MASK 0xffff0000 /* ClkDiv (ILP = 1/(4 * (divisor + 1)) */		#define SYCC_FP 0x00000004
			/* Force ALP (or HT if ALPen is not set */
			#define SYCC_AR 0x00000008
			/* Force HT */
			#define SYCC_HR 0x00000010
			/* ClkDiv (ILP = 1/(4 * (divisor + 1)) */
			#define SYCC_CD_MASK 0xffff0000
	#define SYCC_CD_SHIFT 16		#define SYCC_CD_SHIFT 16

	#define CST4329_SPROM_OTP_SEL_MASK 0x00000003		#define CST4329_SPROM_OTP_SEL_MASK 0x00000003
	#define CST4329_DEFCIS_SEL 0 /* OTP is powered up, use def. CIS, no SPROM */		/* OTP is powered up, use def. CIS, no SPROM */
	#define CST4329_SPROM_SEL 1 /* OTP is powered up, SPROM is present */		#define CST4329_DEFCIS_SEL 0
	#define CST4329_OTP_SEL 2 /* OTP is powered up, no SPROM */		/* OTP is powered up, SPROM is present */
	#define CST4329_OTP_PWRDN 3 /* OTP is powered down, SPROM is present */		#define CST4329_SPROM_SEL 1
			/* OTP is powered up, no SPROM */
			#define CST4329_OTP_SEL 2
			/* OTP is powered down, SPROM is present */
			#define CST4329_OTP_PWRDN 3

	#define CST4329_SPI_SDIO_MODE_MASK 0x00000004		#define CST4329_SPI_SDIO_MODE_MASK 0x00000004
	#define CST4329_SPI_SDIO_MODE_SHIFT 2		#define CST4329_SPI_SDIO_MODE_SHIFT 2

	/* 43224 chip-specific ChipControl register bits */		/* 43224 chip-specific ChipControl register bits */
	#define CCTRL43224_GPIO_TOGGLE 0x8000		#define CCTRL43224_GPIO_TOGGLE 0x8000
	#define CCTRL_43224A0_12MA_LED_DRIVE 0x00F000F0 /* 12 mA drive strength */		/* 12 mA drive strength */
	#define CCTRL_43224B0_12MA_LED_DRIVE 0xF0 /* 12 mA drive strength for later 43224s */		#define CCTRL_43224A0_12MA_LED_DRIVE 0x00F000F0
			/* 12 mA drive strength for later 43224s */
			#define CCTRL_43224B0_12MA_LED_DRIVE 0xF0

	/* 43236 Chip specific ChipStatus register bits */		/* 43236 Chip specific ChipStatus register bits */
	#define CST43236_SFLASH_MASK 0x00000040		#define CST43236_SFLASH_MASK 0x00000040
	@@ -84,23 +104,38 @@
	#define CST43236_BOOT_FROM_INVALID 3		#define CST43236_BOOT_FROM_INVALID 3

	/* 4331 chip-specific ChipControl register bits */		/* 4331 chip-specific ChipControl register bits */
	#define CCTRL4331_BT_COEXIST (1<<0) /* 0 disable */		/* 0 disable */
	#define CCTRL4331_SECI (1<<1) /* 0 SECI is disabled (JATG functional) */		#define CCTRL4331_BT_COEXIST (1<<0)
	#define CCTRL4331_EXT_LNA (1<<2) /* 0 disable */		/* 0 SECI is disabled (JTAG functional) */
	#define CCTRL4331_SPROM_GPIO13_15 (1<<3) /* sprom/gpio13-15 mux */		#define CCTRL4331_SECI (1<<1)
	#define CCTRL4331_EXTPA_EN (1<<4) /* 0 ext pa disable, 1 ext pa enabled */		/* 0 disable */
	#define CCTRL4331_GPIOCLK_ON_SPROMCS (1<<5) /* set drive out GPIO_CLK on sprom_cs pin */		#define CCTRL4331_EXT_LNA (1<<2)
	#define CCTRL4331_PCIE_MDIO_ON_SPROMCS (1<<6) /* use sprom_cs pin as PCIE mdio interface */		/* sprom/gpio13-15 mux */
	#define CCTRL4331_EXTPA_ON_GPIO2_5 (1<<7) /* aband extpa will be at gpio2/5 and sprom_dout */		#define CCTRL4331_SPROM_GPIO13_15 (1<<3)
	#define CCTRL4331_OVR_PIPEAUXCLKEN (1<<8) /* override core control on pipe_AuxClkEnable */		/* 0 ext pa disable, 1 ext pa enabled */
	#define CCTRL4331_OVR_PIPEAUXPWRDOWN (1<<9) /* override core control on pipe_AuxPowerDown */		#define CCTRL4331_EXTPA_EN (1<<4)
	#define CCTRL4331_PCIE_AUXCLKEN (1<<10) /* pcie_auxclkenable */		/* set drive out GPIO_CLK on sprom_cs pin */
	#define CCTRL4331_PCIE_PIPE_PLLDOWN (1<<11) /* pcie_pipe_pllpowerdown */		#define CCTRL4331_GPIOCLK_ON_SPROMCS (1<<5)
	#define CCTRL4331_BT_SHD0_ON_GPIO4 (1<<16) /* enable bt_shd0 at gpio4 */		/* use sprom_cs pin as PCIE mdio interface */
	#define CCTRL4331_BT_SHD1_ON_GPIO5 (1<<17) /* enable bt_shd1 at gpio5 */		#define CCTRL4331_PCIE_MDIO_ON_SPROMCS (1<<6)
			/* aband extpa will be at gpio2/5 and sprom_dout */
			#define CCTRL4331_EXTPA_ON_GPIO2_5 (1<<7)
			/* override core control on pipe_AuxClkEnable */
			#define CCTRL4331_OVR_PIPEAUXCLKEN (1<<8)
			/* override core control on pipe_AuxPowerDown */
			#define CCTRL4331_OVR_PIPEAUXPWRDOWN (1<<9)
			/* pcie_auxclkenable */
			#define CCTRL4331_PCIE_AUXCLKEN (1<<10)
			/* pcie_pipe_pllpowerdown */
			#define CCTRL4331_PCIE_PIPE_PLLDOWN (1<<11)
			/* enable bt_shd0 at gpio4 */
			#define CCTRL4331_BT_SHD0_ON_GPIO4 (1<<16)
			/* enable bt_shd1 at gpio5 */
			#define CCTRL4331_BT_SHD1_ON_GPIO5 (1<<17)

	/* 4331 Chip specific ChipStatus register bits */		/* 4331 Chip specific ChipStatus register bits */
	#define CST4331_XTAL_FREQ 0x00000001 /* crystal frequency 20/40Mhz */		/* crystal frequency 20/40Mhz */
			#define CST4331_XTAL_FREQ 0x00000001
	#define CST4331_SPROM_PRESENT 0x00000002		#define CST4331_SPROM_PRESENT 0x00000002
	#define CST4331_OTP_PRESENT 0x00000004		#define CST4331_OTP_PRESENT 0x00000004
	#define CST4331_LDO_RF 0x00000008		#define CST4331_LDO_RF 0x00000008
	@@ -110,19 +145,26 @@
	#define CST4319_SPI_CPULESSUSB 0x00000001		#define CST4319_SPI_CPULESSUSB 0x00000001
	#define CST4319_SPI_CLK_POL 0x00000002		#define CST4319_SPI_CLK_POL 0x00000002
	#define CST4319_SPI_CLK_PH 0x00000008		#define CST4319_SPI_CLK_PH 0x00000008
	#define CST4319_SPROM_OTP_SEL_MASK 0x000000c0 /* gpio [7:6], SDIO CIS selection */		/* gpio [7:6], SDIO CIS selection */
			#define CST4319_SPROM_OTP_SEL_MASK 0x000000c0
	#define CST4319_SPROM_OTP_SEL_SHIFT 6		#define CST4319_SPROM_OTP_SEL_SHIFT 6
	#define CST4319_DEFCIS_SEL 0x00000000 /* use default CIS, OTP is powered up */		/* use default CIS, OTP is powered up */
	#define CST4319_SPROM_SEL 0x00000040 /* use SPROM, OTP is powered up */		#define CST4319_DEFCIS_SEL 0x00000000
	#define CST4319_OTP_SEL 0x00000080 /* use OTP, OTP is powered up */		/* use SPROM, OTP is powered up */
	#define CST4319_OTP_PWRDN 0x000000c0 /* use SPROM, OTP is powered down */		#define CST4319_SPROM_SEL 0x00000040
	#define CST4319_SDIO_USB_MODE 0x00000100 /* gpio [8], sdio/usb mode */		/* use OTP, OTP is powered up */
			#define CST4319_OTP_SEL 0x00000080
			/* use SPROM, OTP is powered down */
			#define CST4319_OTP_PWRDN 0x000000c0
			/* gpio [8], sdio/usb mode */
			#define CST4319_SDIO_USB_MODE 0x00000100
	#define CST4319_REMAP_SEL_MASK 0x00000600		#define CST4319_REMAP_SEL_MASK 0x00000600
	#define CST4319_ILPDIV_EN 0x00000800		#define CST4319_ILPDIV_EN 0x00000800
	#define CST4319_XTAL_PD_POL 0x00001000		#define CST4319_XTAL_PD_POL 0x00001000
	#define CST4319_LPO_SEL 0x00002000		#define CST4319_LPO_SEL 0x00002000
	#define CST4319_RES_INIT_MODE 0x0000c000		#define CST4319_RES_INIT_MODE 0x0000c000
	#define CST4319_PALDO_EXTPNP 0x00010000 /* PALDO is configured with external PNP */		/* PALDO is configured with external PNP */
			#define CST4319_PALDO_EXTPNP 0x00010000
	#define CST4319_CBUCK_MODE_MASK 0x00060000		#define CST4319_CBUCK_MODE_MASK 0x00060000
	#define CST4319_CBUCK_MODE_BURST 0x00020000		#define CST4319_CBUCK_MODE_BURST 0x00020000
	#define CST4319_CBUCK_MODE_LPBURST 0x00060000		#define CST4319_CBUCK_MODE_LPBURST 0x00060000
	@@ -153,7 +195,8 @@
	#define CST4313_SPROM_OTP_SEL_SHIFT 0		#define CST4313_SPROM_OTP_SEL_SHIFT 0

	/* 4313 Chip specific ChipControl register bits */		/* 4313 Chip specific ChipControl register bits */
	#define CCTRL_4313_12MA_LED_DRIVE 0x00000007 /* 12 mA drive strengh for later 4313 */		/* 12 mA drive strengh for later 4313 */
			#define CCTRL_4313_12MA_LED_DRIVE 0x00000007

	#define BCM47162_DMP() ((sih->chip == BCM47162_CHIP_ID) && \		#define BCM47162_DMP() ((sih->chip == BCM47162_CHIP_ID) && \
	(sih->chiprev == 0) && \		(sih->chiprev == 0) && \
	@@ -227,9 +270,12 @@
	#define SD_SG32 0x00000008		#define SD_SG32 0x00000008
	#define SD_SZ_ALIGN 0x00000fff		#define SD_SZ_ALIGN 0x00000fff

	#define PCI_CFG_GPIO_SCS 0x10 /* PCI config space bit 4 for 4306c0 slow clock source */		/* PCI config space bit 4 for 4306c0 slow clock source */
	#define PCI_CFG_GPIO_XTAL 0x40 /* PCI config space GPIO 14 for Xtal power-up */		#define PCI_CFG_GPIO_SCS 0x10
	#define PCI_CFG_GPIO_PLL 0x80 /* PCI config space GPIO 15 for PLL power-down */		/* PCI config space GPIO 14 for Xtal power-up */
			#define PCI_CFG_GPIO_XTAL 0x40
			/* PCI config space GPIO 15 for PLL power-down */
			#define PCI_CFG_GPIO_PLL 0x80

	/* power control defines */		/* power control defines */
	#define PLL_DELAY 150 /* us pll on delay */		#define PLL_DELAY 150 /* us pll on delay */
	@@ -468,7 +514,8 @@ void ai_scan(struct si_pub sih, void regs)
	}		}
	eromlim = eromptr + (ER_REMAPCONTROL / sizeof(u32));		eromlim = eromptr + (ER_REMAPCONTROL / sizeof(u32));

	SI_VMSG(("ai_scan: regs = 0x%p, erombase = 0x%08x, eromptr = 0x%p, eromlim = 0x%p\n", regs, erombase, eromptr, eromlim));		SI_VMSG(("ai_scan: regs = 0x%p, erombase = 0x%08x, eromptr = 0x%p, "
			"eromlim = 0x%p\n", regs, erombase, eromptr, eromlim));
	while (eromptr < eromlim) {		while (eromptr < eromlim) {
	u32 cia, cib, cid, mfg, crev, nmw, nsw, nmp, nsp;		u32 cia, cib, cid, mfg, crev, nmw, nsw, nmp, nsp;
	u32 mpd, asd, addrl, addrh, sizel, sizeh;		u32 mpd, asd, addrl, addrh, sizel, sizeh;
	@@ -502,7 +549,9 @@ void ai_scan(struct si_pub sih, void regs)
	nmp = (cib & CIB_NMP_MASK) >> CIB_NMP_SHIFT;		nmp = (cib & CIB_NMP_MASK) >> CIB_NMP_SHIFT;
	nsp = (cib & CIB_NSP_MASK) >> CIB_NSP_SHIFT;		nsp = (cib & CIB_NSP_MASK) >> CIB_NSP_SHIFT;

	SI_VMSG(("Found component 0x%04x/0x%04x rev %d at erom addr 0x%p, with nmw = %d, " "nsw = %d, nmp = %d & nsp = %d\n", mfg, cid, crev, base, nmw, nsw, nmp, nsp));		SI_VMSG(("Found component 0x%04x/0x%04x rev %d at erom addr "
			"0x%p, with nmw = %d, nsw = %d, nmp = %d & nsp = %d\n",
			mfg, cid, crev, base, nmw, nsw, nmp, nsp));

	if (((mfg == MFGID_ARM) && (cid == DEF_AI_COMP)) \|\| (nsp == 0))		if (((mfg == MFGID_ARM) && (cid == DEF_AI_COMP)) \|\| (nsp == 0))
	continue;		continue;
	@@ -526,7 +575,8 @@ void ai_scan(struct si_pub sih, void regs)
	for (i = 0; i < nmp; i++) {		for (i = 0; i < nmp; i++) {
	mpd = get_erom_ent(sih, &eromptr, ER_VALID, ER_VALID);		mpd = get_erom_ent(sih, &eromptr, ER_VALID, ER_VALID);
	if ((mpd & ER_TAG) != ER_MP) {		if ((mpd & ER_TAG) != ER_MP) {
	SI_ERROR(("Not enough MP entries for component 0x%x\n", cid));		SI_ERROR(("Not enough MP entries for "
			"component 0x%x\n", cid));
	goto error;		goto error;
	}		}
	SI_VMSG((" Master port %d, mp: %d id: %d\n", i,		SI_VMSG((" Master port %d, mp: %d id: %d\n", i,
	@@ -549,7 +599,8 @@ void ai_scan(struct si_pub sih, void regs)
	br = true;		br = true;
	else if ((addrh != 0) \|\| (sizeh != 0)		else if ((addrh != 0) \|\| (sizeh != 0)
	\|\| (sizel != SI_CORE_SIZE)) {		\|\| (sizel != SI_CORE_SIZE)) {
	SI_ERROR(("First Slave ASD for core 0x%04x malformed " "(0x%08x)\n", cid, asd));		SI_ERROR(("First Slave ASD for core 0x%04x "
			"malformed (0x%08x)\n", cid, asd));
	goto error;		goto error;
	}		}
	}		}
	@@ -704,7 +755,8 @@ u32 ai_addrspace(struct si_pub *sih, uint asidx)
	else if (asidx == 1)		else if (asidx == 1)
	return sii->coresba2[cidx];		return sii->coresba2[cidx];
	else {		else {
	SI_ERROR(("%s: Need to parse the erom again to find addr space %d\n", __func__, asidx));		SI_ERROR(("%s: Need to parse the erom again to find addr "
			"space %d\n", __func__, asidx));
	return 0;		return 0;
	}		}
	}		}
	@@ -723,7 +775,8 @@ u32 ai_addrspacesize(struct si_pub *sih, uint asidx)
	else if (asidx == 1)		else if (asidx == 1)
	return sii->coresba2_size[cidx];		return sii->coresba2_size[cidx];
	else {		else {
	SI_ERROR(("%s: Need to parse the erom again to find addr space %d\n", __func__, asidx));		SI_ERROR(("%s: Need to parse the erom again to find addr "
			"space %d\n", __func__, asidx));
	return 0;		return 0;
	}		}
	}		}
	@@ -735,7 +788,8 @@ uint ai_flag(struct si_pub *sih)

	sii = SI_INFO(sih);		sii = SI_INFO(sih);
	if (BCM47162_DMP()) {		if (BCM47162_DMP()) {
	SI_ERROR(("%s: Attempting to read MIPS DMP registers on 47162a0", __func__));		SI_ERROR(("%s: Attempting to read MIPS DMP registers "
			"on 47162a0", __func__));
	return sii->curidx;		return sii->curidx;
	}		}
	ai = sii->curwrap;		ai = sii->curwrap;
	@@ -833,7 +887,8 @@ u32 ai_core_sflags(struct si_pub *sih, u32 mask, u32 val)

	sii = SI_INFO(sih);		sii = SI_INFO(sih);
	if (BCM47162_DMP()) {		if (BCM47162_DMP()) {
	SI_ERROR(("%s: Accessing MIPS DMP register (iostatus) on 47162a0", __func__));		SI_ERROR(("%s: Accessing MIPS DMP register (iostatus) "
			"on 47162a0", __func__));
	return 0;		return 0;
	}		}

drivers/staging/brcm80211/brcmsmac/aiutils.h

+14 −7

Original line number	Original line	Diff line number	Diff line
	@@ -242,16 +242,23 @@
	#define SRC_PRESENT 0x00000001		#define SRC_PRESENT 0x00000001

	/* 4330 chip-specific ChipStatus register bits */		/* 4330 chip-specific ChipStatus register bits */
	#define CST4330_CHIPMODE_SDIOD(cs) (((cs) & 0x7) < 6) /* SDIO \|\| gSPI */		/* SDIO \|\| gSPI */
	#define CST4330_CHIPMODE_USB20D(cs) (((cs) & 0x7) >= 6) /* USB \|\| USBDA */		#define CST4330_CHIPMODE_SDIOD(cs) (((cs) & 0x7) < 6)
	#define CST4330_CHIPMODE_SDIO(cs) (((cs) & 0x4) == 0) /* SDIO */		/* USB \|\| USBDA */
	#define CST4330_CHIPMODE_GSPI(cs) (((cs) & 0x6) == 4) /* gSPI */		#define CST4330_CHIPMODE_USB20D(cs) (((cs) & 0x7) >= 6)
	#define CST4330_CHIPMODE_USB(cs) (((cs) & 0x7) == 6) /* USB packet-oriented */		/* SDIO */
	#define CST4330_CHIPMODE_USBDA(cs) (((cs) & 0x7) == 7) /* USB Direct Access */		#define CST4330_CHIPMODE_SDIO(cs) (((cs) & 0x4) == 0)
			/* gSPI */
			#define CST4330_CHIPMODE_GSPI(cs) (((cs) & 0x6) == 4)
			/* USB packet-oriented */
			#define CST4330_CHIPMODE_USB(cs) (((cs) & 0x7) == 6)
			/* USB Direct Access */
			#define CST4330_CHIPMODE_USBDA(cs) (((cs) & 0x7) == 7)
	#define CST4330_OTP_PRESENT 0x00000010		#define CST4330_OTP_PRESENT 0x00000010
	#define CST4330_LPO_AUTODET_EN 0x00000020		#define CST4330_LPO_AUTODET_EN 0x00000020
	#define CST4330_ARMREMAP_0 0x00000040		#define CST4330_ARMREMAP_0 0x00000040
	#define CST4330_SPROM_PRESENT 0x00000080 /* takes priority over OTP if both set */		/* takes priority over OTP if both set */
			#define CST4330_SPROM_PRESENT 0x00000080
	#define CST4330_ILPDIV_EN 0x00000100		#define CST4330_ILPDIV_EN 0x00000100
	#define CST4330_LPO_SEL 0x00000200		#define CST4330_LPO_SEL 0x00000200
	#define CST4330_RES_INIT_MODE_SHIFT 10		#define CST4330_RES_INIT_MODE_SHIFT 10

drivers/staging/brcm80211/brcmsmac/ampdu.c

+131 −65

Original line number	Original line	Diff line number	Diff line
	@@ -22,19 +22,32 @@
	#include "main.h"		#include "main.h"
	#include "ampdu.h"		#include "ampdu.h"

	#define AMPDU_MAX_MPDU 32 /* max number of mpdus in an ampdu */		/* max number of mpdus in an ampdu */
	#define AMPDU_NUM_MPDU_LEGACY 16 /* max number of mpdus in an ampdu to a legacy */		#define AMPDU_MAX_MPDU 32
	#define AMPDU_TX_BA_MAX_WSIZE 64 /* max Tx ba window size (in pdu) */		/* max number of mpdus in an ampdu to a legacy */
	#define AMPDU_TX_BA_DEF_WSIZE 64 /* default Tx ba window size (in pdu) */		#define AMPDU_NUM_MPDU_LEGACY 16
	#define AMPDU_RX_BA_DEF_WSIZE 64 /* max Rx ba window size (in pdu) */		/* max Tx ba window size (in pdu) */
	#define AMPDU_RX_BA_MAX_WSIZE 64 /* default Rx ba window size (in pdu) */		#define AMPDU_TX_BA_MAX_WSIZE 64
	#define AMPDU_MAX_DUR 5 /* max dur of tx ampdu (in msec) */		/* default Tx ba window size (in pdu) */
	#define AMPDU_DEF_RETRY_LIMIT 5 /* default tx retry limit */		#define AMPDU_TX_BA_DEF_WSIZE 64
	#define AMPDU_DEF_RR_RETRY_LIMIT 2 /* default tx retry limit at reg rate */		/* default Rx ba window size (in pdu) */
	#define AMPDU_DEF_TXPKT_WEIGHT 2 /* default weight of ampdu in txfifo */		#define AMPDU_RX_BA_DEF_WSIZE 64
	#define AMPDU_DEF_FFPLD_RSVD 2048 /* default ffpld reserved bytes */		/* max Rx ba window size (in pdu) */
	#define AMPDU_INI_FREE 10 /* # of inis to be freed on detach */		#define AMPDU_RX_BA_MAX_WSIZE 64
	#define AMPDU_SCB_MAX_RELEASE 20 /* max # of mpdus released at a time */		/* max dur of tx ampdu (in msec) */
			#define AMPDU_MAX_DUR 5
			/* default tx retry limit */
			#define AMPDU_DEF_RETRY_LIMIT 5
			/* default tx retry limit at reg rate */
			#define AMPDU_DEF_RR_RETRY_LIMIT 2
			/* default weight of ampdu in txfifo */
			#define AMPDU_DEF_TXPKT_WEIGHT 2
			/* default ffpld reserved bytes */
			#define AMPDU_DEF_FFPLD_RSVD 2048
			/* # of inis to be freed on detach */
			#define AMPDU_INI_FREE 10
			/* max # of mpdus released at a time */
			#define AMPDU_SCB_MAX_RELEASE 20

	#define NUM_FFPLD_FIFO 4 /* number of fifo concerned by pre-loading */		#define NUM_FFPLD_FIFO 4 /* number of fifo concerned by pre-loading */
	#define FFPLD_TX_MAX_UNFL 200 /* default value of the average number of ampdu		#define FFPLD_TX_MAX_UNFL 200 /* default value of the average number of ampdu
	@@ -59,44 +72,70 @@
	* some counters might be redundant with the ones in wlc or ampdu structures.		* some counters might be redundant with the ones in wlc or ampdu structures.
	* This allows to maintain a specific state independently of		* This allows to maintain a specific state independently of
	* how often and/or when the wlc counters are updated.		* how often and/or when the wlc counters are updated.
			*
			* ampdu_pld_size: number of bytes to be pre-loaded
			* mcs2ampdu_table: per-mcs max # of mpdus in an ampdu
			* prev_txfunfl: num of underflows last read from the HW macstats counter
			* accum_txfunfl: num of underflows since we modified pld params
			* accum_txampdu: num of tx ampdu since we modified pld params
			* prev_txampdu: previous reading of tx ampdu
			* dmaxferrate: estimated dma avg xfer rate in kbits/sec
	*/		*/
	struct brcms_fifo_info {		struct brcms_fifo_info {
	u16 ampdu_pld_size; /* number of bytes to be pre-loaded */		u16 ampdu_pld_size;
	u8 mcs2ampdu_table[FFPLD_MAX_MCS + 1]; /* per-mcs max # of mpdus in an ampdu */		u8 mcs2ampdu_table[FFPLD_MAX_MCS + 1];
	u16 prev_txfunfl; /* num of underflows last read from the HW macstats counter */		u16 prev_txfunfl;
	u32 accum_txfunfl; /* num of underflows since we modified pld params */		u32 accum_txfunfl;
	u32 accum_txampdu; /* num of tx ampdu since we modified pld params */		u32 accum_txampdu;
	u32 prev_txampdu; /* previous reading of tx ampdu */		u32 prev_txampdu;
	u32 dmaxferrate; /* estimated dma avg xfer rate in kbits/sec */		u32 dmaxferrate;
	};		};

	/* AMPDU module specific state */		/* AMPDU module specific state
	struct ampdu_info {		*
	struct brcms_c_info wlc; / pointer to main wlc structure */		* wlc: pointer to main wlc structure
	int scb_handle; /* scb cubby handle to retrieve data from scb */		* scb_handle: scb cubby handle to retrieve data from scb
	u8 ini_enable[AMPDU_MAX_SCB_TID]; /* per-tid initiator enable/disable of ampdu */		* ini_enable: per-tid initiator enable/disable of ampdu
	u8 ba_tx_wsize; /* Tx ba window size (in pdu) */		* ba_tx_wsize: Tx ba window size (in pdu)
	u8 ba_rx_wsize; /* Rx ba window size (in pdu) */		* ba_rx_wsize: Rx ba window size (in pdu)
	u8 retry_limit; /* mpdu transmit retry limit */		* retry_limit: mpdu transmit retry limit
	u8 rr_retry_limit; /* mpdu transmit retry limit at regular rate */		* rr_retry_limit: mpdu transmit retry limit at regular rate
	u8 retry_limit_tid[AMPDU_MAX_SCB_TID]; /* per-tid mpdu transmit retry limit */		* retry_limit_tid: per-tid mpdu transmit retry limit
	/* per-tid mpdu transmit retry limit at regular rate */		* rr_retry_limit_tid: per-tid mpdu transmit retry limit at regular rate
	u8 rr_retry_limit_tid[AMPDU_MAX_SCB_TID];		* mpdu_density: min mpdu spacing (0-7) ==> 2^(x-1)/8 usec
	u8 mpdu_density; /* min mpdu spacing (0-7) ==> 2^(x-1)/8 usec */		* max_pdu: max pdus allowed in ampdu
	s8 max_pdu; /* max pdus allowed in ampdu */		* dur: max duration of an ampdu (in msec)
	u8 dur; /* max duration of an ampdu (in msec) */		* txpkt_weight: weight of ampdu in txfifo; reduces rate lag
	u8 txpkt_weight; /* weight of ampdu in txfifo; reduces rate lag */		* rx_factor: maximum rx ampdu factor (0-3) ==> 2^(13+x) bytes
	u8 rx_factor; /* maximum rx ampdu factor (0-3) ==> 2^(13+x) bytes */		* ffpld_rsvd: number of bytes to reserve for preload
	u32 ffpld_rsvd; /* number of bytes to reserve for preload */		* max_txlen: max size of ampdu per mcs, bw and sgi
	u32 max_txlen[MCS_TABLE_SIZE][2][2]; /* max size of ampdu per mcs, bw and sgi */		* ini_free: array of ini's to be freed on detach
	void ini_free[AMPDU_INI_FREE]; / array of ini's to be freed on detach */		* mfbr: enable multiple fallback rate
	bool mfbr; /* enable multiple fallback rate */		* tx_max_funl: underflows should be kept such that
	u32 tx_max_funl; /* underflows should be kept such that
	* (tx_max_funfl*underflows) < tx frames		* (tx_max_funfl*underflows) < tx frames
			* fifo_tb: table of fifo infos
	*/		*/
	/* table of fifo infos */		struct ampdu_info {
			struct brcms_c_info *wlc;
			int scb_handle;
			u8 ini_enable[AMPDU_MAX_SCB_TID];
			u8 ba_tx_wsize;
			u8 ba_rx_wsize;
			u8 retry_limit;
			u8 rr_retry_limit;
			u8 retry_limit_tid[AMPDU_MAX_SCB_TID];
			u8 rr_retry_limit_tid[AMPDU_MAX_SCB_TID];
			u8 mpdu_density;
			s8 max_pdu;
			u8 dur;
			u8 txpkt_weight;
			u8 rx_factor;
			u32 ffpld_rsvd;
			u32 max_txlen[MCS_TABLE_SIZE][2][2];
			void *ini_free[AMPDU_INI_FREE];
			bool mfbr;
			u32 tx_max_funl;
	struct brcms_fifo_info fifo_tb[NUM_FFPLD_FIFO];		struct brcms_fifo_info fifo_tb[NUM_FFPLD_FIFO];

	};		};

	/* used for flushing ampdu packets */		/* used for flushing ampdu packets */
	@@ -163,7 +202,10 @@ struct ampdu_info brcms_c_ampdu_attach(struct brcms_c_info wlc)
	ampdu->txpkt_weight = AMPDU_DEF_TXPKT_WEIGHT;		ampdu->txpkt_weight = AMPDU_DEF_TXPKT_WEIGHT;

	ampdu->ffpld_rsvd = AMPDU_DEF_FFPLD_RSVD;		ampdu->ffpld_rsvd = AMPDU_DEF_FFPLD_RSVD;
	/* bump max ampdu rcv size to 64k for all 11n devices except 4321A0 and 4321A1 */		/*
			* bump max ampdu rcv size to 64k for all 11n
			* devices except 4321A0 and 4321A1
			*/
	if (BRCMS_ISNPHY(wlc->band) && NREV_LT(wlc->band->phyrev, 2))		if (BRCMS_ISNPHY(wlc->band) && NREV_LT(wlc->band->phyrev, 2))
	ampdu->rx_factor = IEEE80211_HT_MAX_AMPDU_32K;		ampdu->rx_factor = IEEE80211_HT_MAX_AMPDU_32K;
	else		else
	@@ -194,7 +236,10 @@ void brcms_c_ampdu_detach(struct ampdu_info *ampdu)
	if (!ampdu)		if (!ampdu)
	return;		return;

	/* free all ini's which were to be freed on callbacks which were never called */		/*
			* free all ini's which were to be freed on
			* callbacks which were never called
			*/
	for (i = 0; i < AMPDU_INI_FREE; i++)		for (i = 0; i < AMPDU_INI_FREE; i++)
	kfree(ampdu->ini_free[i]);		kfree(ampdu->ini_free[i]);

	@@ -220,7 +265,8 @@ static void brcms_c_scb_ampdu_update_config(struct ampdu_info *ampdu,
	if (ampdu->max_pdu != AUTO)		if (ampdu->max_pdu != AUTO)
	scb_ampdu->max_pdu = (u8) ampdu->max_pdu;		scb_ampdu->max_pdu = (u8) ampdu->max_pdu;

	scb_ampdu->release = min_t(u8, scb_ampdu->max_pdu, AMPDU_SCB_MAX_RELEASE);		scb_ampdu->release = min_t(u8, scb_ampdu->max_pdu,
			AMPDU_SCB_MAX_RELEASE);

	if (scb_ampdu->max_rx_ampdu_bytes)		if (scb_ampdu->max_rx_ampdu_bytes)
	scb_ampdu->release = min_t(u8, scb_ampdu->release,		scb_ampdu->release = min_t(u8, scb_ampdu->release,
	@@ -321,8 +367,8 @@ static int brcms_c_ffpld_check_txfunfl(struct brcms_c_info *wlc, int fid)

	return 0;		return 0;
	}		}
	max_mpdu =		max_mpdu = min_t(u8, fifo->mcs2ampdu_table[FFPLD_MAX_MCS],
	min_t(u8, fifo->mcs2ampdu_table[FFPLD_MAX_MCS], AMPDU_NUM_MPDU_LEGACY);		AMPDU_NUM_MPDU_LEGACY);

	/* In case max value max_pdu is already lower than		/* In case max value max_pdu is already lower than
	the fifo depth, there is nothing more we can do.		the fifo depth, there is nothing more we can do.
	@@ -344,11 +390,12 @@ static int brcms_c_ffpld_check_txfunfl(struct brcms_c_info *wlc, int fid)
	brcms_c_scb_ampdu_update_config_all(ampdu);		brcms_c_scb_ampdu_update_config_all(ampdu);

	/*		/*
	compute a new dma xfer rate for max_mpdu @ max mcs.		* compute a new dma xfer rate for max_mpdu @ max mcs.
	This is the minimum dma rate that		* This is the minimum dma rate that can achieve no
	can achieve no underflow condition for the current mpdu size.		* underflow condition for the current mpdu size.
			*
			* note : we divide/multiply by 100 to avoid integer overflows
	*/		*/
	/* note : we divide/multiply by 100 to avoid integer overflows */
	fifo->dmaxferrate =		fifo->dmaxferrate =
	(((phy_rate / 100) *		(((phy_rate / 100) *
	(max_mpdu * FFPLD_MPDU_SIZE - fifo->ampdu_pld_size))		(max_mpdu * FFPLD_MPDU_SIZE - fifo->ampdu_pld_size))
	@@ -387,8 +434,8 @@ static void brcms_c_ffpld_calc_mcs2ampdu_table(struct ampdu_info *ampdu, int f)

	/* recompute the dma rate */		/* recompute the dma rate */
	/* note : we divide/multiply by 100 to avoid integer overflows */		/* note : we divide/multiply by 100 to avoid integer overflows */
	max_mpdu =		max_mpdu = min_t(u8, fifo->mcs2ampdu_table[FFPLD_MAX_MCS],
	min_t(u8, fifo->mcs2ampdu_table[FFPLD_MAX_MCS], AMPDU_NUM_MPDU_LEGACY);		AMPDU_NUM_MPDU_LEGACY);
	phy_rate = MCS_RATE(FFPLD_MAX_MCS, true, false);		phy_rate = MCS_RATE(FFPLD_MAX_MCS, true, false);
	dma_rate =		dma_rate =
	(((phy_rate / 100) *		(((phy_rate / 100) *
	@@ -666,9 +713,13 @@ brcms_c_sendampdu(struct ampdu_info ampdu, struct brcms_txq_info qi,
	if (count == scb_ampdu->max_pdu)		if (count == scb_ampdu->max_pdu)
	break;		break;

	/* check to see if the next pkt is a candidate for aggregation */		/*
			* check to see if the next pkt is
			* a candidate for aggregation
			*/
	p = pktq_ppeek(&qi->q, prec);		p = pktq_ppeek(&qi->q, prec);
	tx_info = IEEE80211_SKB_CB(p); /* tx_info must be checked with current p */		/* tx_info must be checked with current p */
			tx_info = IEEE80211_SKB_CB(p);

	if (p) {		if (p) {
	if ((tx_info->flags & IEEE80211_TX_CTL_AMPDU) &&		if ((tx_info->flags & IEEE80211_TX_CTL_AMPDU) &&
	@@ -683,7 +734,10 @@ brcms_c_sendampdu(struct ampdu_info ampdu, struct brcms_txq_info qi,
	continue;		continue;
	}		}

	/* check if there are enough descriptors available */		/*
			* check if there are enough
			* descriptors available
			*/
	if (TXAVAIL(wlc, fifo) <= (seg_cnt + 1)) {		if (TXAVAIL(wlc, fifo) <= (seg_cnt + 1)) {
	wiphy_err(wiphy, "%s: No fifo space "		wiphy_err(wiphy, "%s: No fifo space "
	"!!\n", __func__);		"!!\n", __func__);
	@@ -962,10 +1016,13 @@ brcms_c_ampdu_dotxstatus_complete(struct ampdu_info ampdu, struct scb scb,
	supr_status == TX_STATUS_SUPR_EXPTIME) {		supr_status == TX_STATUS_SUPR_EXPTIME) {
	retry = false;		retry = false;
	} else if (supr_status == TX_STATUS_SUPR_EXPTIME) {		} else if (supr_status == TX_STATUS_SUPR_EXPTIME) {
	/* TX underflow : try tuning pre-loading or ampdu size */		/* TX underflow:
			* try tuning pre-loading or ampdu size
			*/
	} else if (supr_status == TX_STATUS_SUPR_FRAG) {		} else if (supr_status == TX_STATUS_SUPR_FRAG) {
	/* if there were underflows, but pre-loading is not active,		/*
	notify rate adaptation.		* if there were underflows, but pre-loading
			* is not active, notify rate adaptation.
	*/		*/
	if (brcms_c_ffpld_check_txfunfl(wlc,		if (brcms_c_ffpld_check_txfunfl(wlc,
	prio2fifo[tid]) > 0)		prio2fifo[tid]) > 0)
	@@ -1013,7 +1070,10 @@ brcms_c_ampdu_dotxstatus_complete(struct ampdu_info ampdu, struct scb scb,
	ini->tx_in_transit--;		ini->tx_in_transit--;
	ini->txretry[index] = 0;		ini->txretry[index] = 0;

	/* ampdu_ack_len: number of acked aggregated frames */		/*
			* ampdu_ack_len:
			* number of acked aggregated frames
			*/
	/* ampdu_len: number of aggregated frames */		/* ampdu_len: number of aggregated frames */
	brcms_c_ampdu_rate_status(wlc, tx_info, txs,		brcms_c_ampdu_rate_status(wlc, tx_info, txs,
	mcs);		mcs);
	@@ -1038,7 +1098,10 @@ brcms_c_ampdu_dotxstatus_complete(struct ampdu_info ampdu, struct scb scb,
	if (retry && (txrate[0].count < (int)retry_limit)) {		if (retry && (txrate[0].count < (int)retry_limit)) {
	ini->txretry[index]++;		ini->txretry[index]++;
	ini->tx_in_transit--;		ini->tx_in_transit--;
	/* Use high prededence for retransmit to give some punch */		/*
			* Use high prededence for retransmit to
			* give some punch
			*/
	/* brcms_c_txq_enq(wlc, scb, p,		/* brcms_c_txq_enq(wlc, scb, p,
	* BRCMS_PRIO_TO_PREC(tid)); */		* BRCMS_PRIO_TO_PREC(tid)); */
	brcms_c_txq_enq(wlc, scb, p,		brcms_c_txq_enq(wlc, scb, p,
	@@ -1150,7 +1213,10 @@ void brcms_c_ampdu_shm_upd(struct ampdu_info *ampdu)
	{		{
	struct brcms_c_info *wlc = ampdu->wlc;		struct brcms_c_info *wlc = ampdu->wlc;

	/* Extend ucode internal watchdog timer to match larger received frames */		/*
			* Extend ucode internal watchdog timer to
			* match larger received frames
			*/
	if ((ampdu->rx_factor & IEEE80211_HT_AMPDU_PARM_FACTOR) ==		if ((ampdu->rx_factor & IEEE80211_HT_AMPDU_PARM_FACTOR) ==
	IEEE80211_HT_MAX_AMPDU_64K) {		IEEE80211_HT_MAX_AMPDU_64K) {
	brcms_c_write_shm(wlc, M_MIMO_MAXSYM, MIMO_MAXSYM_MAX);		brcms_c_write_shm(wlc, M_MIMO_MAXSYM, MIMO_MAXSYM_MAX);