Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 41494cba authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'drm-intel-fixes' of git://people.freedesktop.org/~danvet/drm-intel into drm-next 

Daniel writes:

"- Regression fixer for an OOPS at boot when i915.ko is built-in and
  CONFIG_PM=n, introduce in 3.5 (patch from Hunt Xu)
- Regression fixer for occlusion query failures, the required w/a wasn't
  applied in all cases (thanks to Eric for tracking this on down).
- dmar vs. dma_buf imprt fix (Dave Airlie)
- 2 patches to fight down forcewake issues on snb. This is the stuff I've
  talked about 2 weeks ago already, it's a minefield. Investigation still
  going on, but afaict this is the best we have for now.
- a few minor things to keep coverty&compiler happy (Alan, Davendra,
  Stéphane)
- tons of hsw pci ids - this one is a bit late because internal approval
  sometimes takes a while, but ppl in charge finally agreed that world+dog
  already knows about ult and crw haswell variants ;-)

Wrt regressions I'm aware of:
- the power regression due to semaphores=1. Ben is running around with a
  killawatt, unfortunately we have a hard time reproducing this one. And
  this /shouldn't/ increase power usage. Ben has turned up a few odds bits
  though already.
- the lvds fix in 3.6-rc1 broke a backlight after lid close/open (but can
  be resurrected with a modeset cycle). I guess we anger the bios - I'm
  still looking into this one.
- gmbus broke edid reading on an odd-ball monitor, we need to fall-back.
  Due to vacation (both mine&the reporter's) this is stalling for a final
  patch and a tested-by on it. But issue is fully diagnosed."

* 'drm-intel-fixes' of git://people.freedesktop.org/~danvet/drm-intel:
  drm/i915: correctly order the ring init sequence
  drm/i915: add more Haswell PCI IDs
  drm/i915: make rc6 in sysfs functions conditional
  drm/i915: Workaround hang with BSD and forcewake on SandyBridge
  drm/i915: Make intel_panel_get_backlight static.
  i915: don't map imported dma-bufs for dmar.
  drm/i915: remove unused variable
  drm/i915: Don't forget to apply SNB PIPE_CONTROL GTT workaround.
  drm/i915: fix forcewake related hangs on snb
  i915: Remove silly test
  i915: fix error path leak in intel_sdvo_write_cmd
  vlv: it might be wise if we initialised the flag value...
parents 0f457e48 0d8957c8

drivers/char/agp/intel-agp.h

+34 −5
Original line number Diff line number Diff line
@@ -242,13 +242,42 @@ 
#define PCI_DEVICE_ID_INTEL_HASWELL_HB			0x0400 /* Desktop */

#define PCI_DEVICE_ID_INTEL_HASWELL_D_GT1_IG		0x0402

#define PCI_DEVICE_ID_INTEL_HASWELL_D_GT2_IG		0x0412

#define PCI_DEVICE_ID_INTEL_HASWELL_D_GT2_PLUS_IG	0x0422

#define PCI_DEVICE_ID_INTEL_HASWELL_M_HB		0x0404 /* Mobile */

#define PCI_DEVICE_ID_INTEL_HASWELL_M_GT1_IG		0x0406

#define PCI_DEVICE_ID_INTEL_HASWELL_M_GT2_IG		0x0416

#define PCI_DEVICE_ID_INTEL_HASWELL_M_GT2_PLUS_IG	0x0426

#define PCI_DEVICE_ID_INTEL_HASWELL_S_HB		0x0408 /* Server */

#define PCI_DEVICE_ID_INTEL_HASWELL_S_GT1_IG		0x040a

#define PCI_DEVICE_ID_INTEL_HASWELL_S_GT2_IG		0x041a

#define PCI_DEVICE_ID_INTEL_HASWELL_SDV		0x0c16 /* SDV */

#define PCI_DEVICE_ID_INTEL_HASWELL_S_GT2_PLUS_IG	0x042a

#define PCI_DEVICE_ID_INTEL_HASWELL_E_HB		0x0c04

#define PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT1_IG	0x0C02

#define PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT2_IG	0x0C12

#define PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT2_PLUS_IG	0x0C22

#define PCI_DEVICE_ID_INTEL_HASWELL_SDV_M_GT1_IG	0x0C06

#define PCI_DEVICE_ID_INTEL_HASWELL_SDV_M_GT2_IG	0x0C16

#define PCI_DEVICE_ID_INTEL_HASWELL_SDV_M_GT2_PLUS_IG	0x0C26

#define PCI_DEVICE_ID_INTEL_HASWELL_SDV_S_GT1_IG	0x0C0A

#define PCI_DEVICE_ID_INTEL_HASWELL_SDV_S_GT2_IG	0x0C1A

#define PCI_DEVICE_ID_INTEL_HASWELL_SDV_S_GT2_PLUS_IG	0x0C2A

#define PCI_DEVICE_ID_INTEL_HASWELL_ULT_D_GT1_IG	0x0A02

#define PCI_DEVICE_ID_INTEL_HASWELL_ULT_D_GT2_IG	0x0A12

#define PCI_DEVICE_ID_INTEL_HASWELL_ULT_D_GT2_PLUS_IG	0x0A22

#define PCI_DEVICE_ID_INTEL_HASWELL_ULT_M_GT1_IG	0x0A06

#define PCI_DEVICE_ID_INTEL_HASWELL_ULT_M_GT2_IG	0x0A16

#define PCI_DEVICE_ID_INTEL_HASWELL_ULT_M_GT2_PLUS_IG	0x0A26

#define PCI_DEVICE_ID_INTEL_HASWELL_ULT_S_GT1_IG	0x0A0A

#define PCI_DEVICE_ID_INTEL_HASWELL_ULT_S_GT2_IG	0x0A1A

#define PCI_DEVICE_ID_INTEL_HASWELL_ULT_S_GT2_PLUS_IG	0x0A2A

#define PCI_DEVICE_ID_INTEL_HASWELL_CRW_D_GT1_IG	0x0D12

#define PCI_DEVICE_ID_INTEL_HASWELL_CRW_D_GT2_IG	0x0D22

#define PCI_DEVICE_ID_INTEL_HASWELL_CRW_D_GT2_PLUS_IG	0x0D32

#define PCI_DEVICE_ID_INTEL_HASWELL_CRW_M_GT1_IG	0x0D16

#define PCI_DEVICE_ID_INTEL_HASWELL_CRW_M_GT2_IG	0x0D26

#define PCI_DEVICE_ID_INTEL_HASWELL_CRW_M_GT2_PLUS_IG	0x0D36

#define PCI_DEVICE_ID_INTEL_HASWELL_CRW_S_GT1_IG	0x0D1A

#define PCI_DEVICE_ID_INTEL_HASWELL_CRW_S_GT2_IG	0x0D2A

#define PCI_DEVICE_ID_INTEL_HASWELL_CRW_S_GT2_PLUS_IG	0x0D3A



#endif

drivers/char/agp/intel-gtt.c

+59 −1
Original line number Diff line number Diff line
@@ -1502,15 +1502,73 @@ static const struct intel_gtt_driver_description { 
	    "Haswell", &sandybridge_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_D_GT2_IG,

	    "Haswell", &sandybridge_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_D_GT2_PLUS_IG,

	    "Haswell", &sandybridge_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_M_GT1_IG,

	    "Haswell", &sandybridge_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_M_GT2_IG,

	    "Haswell", &sandybridge_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_M_GT2_PLUS_IG,

	    "Haswell", &sandybridge_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_S_GT1_IG,

	    "Haswell", &sandybridge_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_S_GT2_IG,

	    "Haswell", &sandybridge_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_SDV,

	{ PCI_DEVICE_ID_INTEL_HASWELL_S_GT2_PLUS_IG,

	    "Haswell", &sandybridge_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT1_IG,

	    "Haswell", &sandybridge_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT2_IG,

	    "Haswell", &sandybridge_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT2_PLUS_IG,

	    "Haswell", &sandybridge_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_SDV_M_GT1_IG,

	    "Haswell", &sandybridge_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_SDV_M_GT2_IG,

	    "Haswell", &sandybridge_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_SDV_M_GT2_PLUS_IG,

	    "Haswell", &sandybridge_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_SDV_S_GT1_IG,

	    "Haswell", &sandybridge_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_SDV_S_GT2_IG,

	    "Haswell", &sandybridge_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_SDV_S_GT2_PLUS_IG,

	    "Haswell", &sandybridge_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_ULT_D_GT1_IG,

	    "Haswell", &sandybridge_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_ULT_D_GT2_IG,

	    "Haswell", &sandybridge_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_ULT_D_GT2_PLUS_IG,

	    "Haswell", &sandybridge_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_ULT_M_GT1_IG,

	    "Haswell", &sandybridge_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_ULT_M_GT2_IG,

	    "Haswell", &sandybridge_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_ULT_M_GT2_PLUS_IG,

	    "Haswell", &sandybridge_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_ULT_S_GT1_IG,

	    "Haswell", &sandybridge_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_ULT_S_GT2_IG,

	    "Haswell", &sandybridge_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_ULT_S_GT2_PLUS_IG,

	    "Haswell", &sandybridge_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_CRW_D_GT1_IG,

	    "Haswell", &sandybridge_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_CRW_D_GT2_IG,

	    "Haswell", &sandybridge_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_CRW_D_GT2_PLUS_IG,

	    "Haswell", &sandybridge_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_CRW_M_GT1_IG,

	    "Haswell", &sandybridge_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_CRW_M_GT2_IG,

	    "Haswell", &sandybridge_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_CRW_M_GT2_PLUS_IG,

	    "Haswell", &sandybridge_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_CRW_S_GT1_IG,

	    "Haswell", &sandybridge_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_CRW_S_GT2_IG,

	    "Haswell", &sandybridge_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_CRW_S_GT2_PLUS_IG,

	    "Haswell", &sandybridge_gtt_driver },

	{ 0, NULL, NULL }

};

drivers/gpu/drm/i915/i915_drv.c

+30 −1
Original line number Diff line number Diff line
@@ -346,11 +346,40 @@ static const struct pci_device_id pciidlist[] = { /* aka */ 
	INTEL_VGA_DEVICE(0x016a, &intel_ivybridge_d_info), /* GT2 server */

	INTEL_VGA_DEVICE(0x0402, &intel_haswell_d_info), /* GT1 desktop */

	INTEL_VGA_DEVICE(0x0412, &intel_haswell_d_info), /* GT2 desktop */

	INTEL_VGA_DEVICE(0x0422, &intel_haswell_d_info), /* GT2 desktop */

	INTEL_VGA_DEVICE(0x040a, &intel_haswell_d_info), /* GT1 server */

	INTEL_VGA_DEVICE(0x041a, &intel_haswell_d_info), /* GT2 server */

	INTEL_VGA_DEVICE(0x042a, &intel_haswell_d_info), /* GT2 server */

	INTEL_VGA_DEVICE(0x0406, &intel_haswell_m_info), /* GT1 mobile */

	INTEL_VGA_DEVICE(0x0416, &intel_haswell_m_info), /* GT2 mobile */

	INTEL_VGA_DEVICE(0x0c16, &intel_haswell_d_info), /* SDV */

	INTEL_VGA_DEVICE(0x0426, &intel_haswell_m_info), /* GT2 mobile */

	INTEL_VGA_DEVICE(0x0C02, &intel_haswell_d_info), /* SDV GT1 desktop */

	INTEL_VGA_DEVICE(0x0C12, &intel_haswell_d_info), /* SDV GT2 desktop */

	INTEL_VGA_DEVICE(0x0C22, &intel_haswell_d_info), /* SDV GT2 desktop */

	INTEL_VGA_DEVICE(0x0C0A, &intel_haswell_d_info), /* SDV GT1 server */

	INTEL_VGA_DEVICE(0x0C1A, &intel_haswell_d_info), /* SDV GT2 server */

	INTEL_VGA_DEVICE(0x0C2A, &intel_haswell_d_info), /* SDV GT2 server */

	INTEL_VGA_DEVICE(0x0C06, &intel_haswell_m_info), /* SDV GT1 mobile */

	INTEL_VGA_DEVICE(0x0C16, &intel_haswell_m_info), /* SDV GT2 mobile */

	INTEL_VGA_DEVICE(0x0C26, &intel_haswell_m_info), /* SDV GT2 mobile */

	INTEL_VGA_DEVICE(0x0A02, &intel_haswell_d_info), /* ULT GT1 desktop */

	INTEL_VGA_DEVICE(0x0A12, &intel_haswell_d_info), /* ULT GT2 desktop */

	INTEL_VGA_DEVICE(0x0A22, &intel_haswell_d_info), /* ULT GT2 desktop */

	INTEL_VGA_DEVICE(0x0A0A, &intel_haswell_d_info), /* ULT GT1 server */

	INTEL_VGA_DEVICE(0x0A1A, &intel_haswell_d_info), /* ULT GT2 server */

	INTEL_VGA_DEVICE(0x0A2A, &intel_haswell_d_info), /* ULT GT2 server */

	INTEL_VGA_DEVICE(0x0A06, &intel_haswell_m_info), /* ULT GT1 mobile */

	INTEL_VGA_DEVICE(0x0A16, &intel_haswell_m_info), /* ULT GT2 mobile */

	INTEL_VGA_DEVICE(0x0A26, &intel_haswell_m_info), /* ULT GT2 mobile */

	INTEL_VGA_DEVICE(0x0D12, &intel_haswell_d_info), /* CRW GT1 desktop */

	INTEL_VGA_DEVICE(0x0D22, &intel_haswell_d_info), /* CRW GT2 desktop */

	INTEL_VGA_DEVICE(0x0D32, &intel_haswell_d_info), /* CRW GT2 desktop */

	INTEL_VGA_DEVICE(0x0D1A, &intel_haswell_d_info), /* CRW GT1 server */

	INTEL_VGA_DEVICE(0x0D2A, &intel_haswell_d_info), /* CRW GT2 server */

	INTEL_VGA_DEVICE(0x0D3A, &intel_haswell_d_info), /* CRW GT2 server */

	INTEL_VGA_DEVICE(0x0D16, &intel_haswell_m_info), /* CRW GT1 mobile */

	INTEL_VGA_DEVICE(0x0D26, &intel_haswell_m_info), /* CRW GT2 mobile */

	INTEL_VGA_DEVICE(0x0D36, &intel_haswell_m_info), /* CRW GT2 mobile */

	INTEL_VGA_DEVICE(0x0f30, &intel_valleyview_m_info),

	INTEL_VGA_DEVICE(0x0157, &intel_valleyview_m_info),

	INTEL_VGA_DEVICE(0x0155, &intel_valleyview_d_info),

drivers/gpu/drm/i915/i915_gem_context.c

+0 −1
Original line number Diff line number Diff line
@@ -451,7 +451,6 @@ int i915_switch_context(struct intel_ring_buffer *ring, 
	struct drm_i915_file_private *file_priv = NULL;

	struct i915_hw_context *to;

	struct drm_i915_gem_object *from_obj = ring->last_context_obj;

	int ret;



	if (dev_priv->hw_contexts_disabled)

		return 0;

drivers/gpu/drm/i915/i915_gem_execbuffer.c

+10 −10
Original line number Diff line number Diff line
@@ -291,6 +291,16 @@ i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj, 
	target_i915_obj = to_intel_bo(target_obj);

	target_offset = target_i915_obj->gtt_offset;



	/* Sandybridge PPGTT errata: We need a global gtt mapping for MI and

	 * pipe_control writes because the gpu doesn't properly redirect them

	 * through the ppgtt for non_secure batchbuffers. */

	if (unlikely(IS_GEN6(dev) &&

	    reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION &&

	    !target_i915_obj->has_global_gtt_mapping)) {

		i915_gem_gtt_bind_object(target_i915_obj,

					 target_i915_obj->cache_level);

	}



	/* The target buffer should have appeared before us in the

	 * exec_object list, so it should have a GTT space bound by now.

	 */
@@ -399,16 +409,6 @@ i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj, 
		io_mapping_unmap_atomic(reloc_page);

	}



	/* Sandybridge PPGTT errata: We need a global gtt mapping for MI and

	 * pipe_control writes because the gpu doesn't properly redirect them

	 * through the ppgtt for non_secure batchbuffers. */

	if (unlikely(IS_GEN6(dev) &&

	    reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION &&

	    !target_i915_obj->has_global_gtt_mapping)) {

		i915_gem_gtt_bind_object(target_i915_obj,

					 target_i915_obj->cache_level);

	}



	/* and update the user's relocation entry */

	reloc->presumed_offset = target_offset;