Loading qcom/sdm660-common.dtsi +22 −0 Original line number Diff line number Diff line Loading @@ -36,6 +36,28 @@ qcom,instance-type = "ufs"; }; sdcc1_ice: sdcc1ice@c0c8000 { compatible = "qcom,ice"; reg = <0xc0c8000 0x8000>; qcom,enable-ice-clk; clock-names = "ice_core_clk_src", "ice_core_clk", "bus_clk", "iface_clk"; clocks = <&clock_gcc SDCC1_ICE_CORE_CLK_SRC>, <&clock_gcc GCC_SDCC1_ICE_CORE_CLK>, <&clock_gcc GCC_SDCC1_APPS_CLK>, <&clock_gcc GCC_SDCC1_AHB_CLK>; qcom,op-freq-hz = <300000000>, <0>, <0>, <0>; qcom,msm-bus,name = "sdcc_ice_noc"; qcom,msm-bus,num-cases = <2>; qcom,msm-bus,num-paths = <1>; qcom,msm-bus,vectors-KBps = <78 512 0 0>, /* No vote */ <78 512 1000 0>; /* Max. bandwidth */ qcom,bus-vector-names = "MIN", "MAX"; qcom,instance-type = "sdcc"; }; ufs1: ufshc@1da4000 { compatible = "qcom,ufshc"; reg = <0x1da4000 0x3000>; Loading Loading
qcom/sdm660-common.dtsi +22 −0 Original line number Diff line number Diff line Loading @@ -36,6 +36,28 @@ qcom,instance-type = "ufs"; }; sdcc1_ice: sdcc1ice@c0c8000 { compatible = "qcom,ice"; reg = <0xc0c8000 0x8000>; qcom,enable-ice-clk; clock-names = "ice_core_clk_src", "ice_core_clk", "bus_clk", "iface_clk"; clocks = <&clock_gcc SDCC1_ICE_CORE_CLK_SRC>, <&clock_gcc GCC_SDCC1_ICE_CORE_CLK>, <&clock_gcc GCC_SDCC1_APPS_CLK>, <&clock_gcc GCC_SDCC1_AHB_CLK>; qcom,op-freq-hz = <300000000>, <0>, <0>, <0>; qcom,msm-bus,name = "sdcc_ice_noc"; qcom,msm-bus,num-cases = <2>; qcom,msm-bus,num-paths = <1>; qcom,msm-bus,vectors-KBps = <78 512 0 0>, /* No vote */ <78 512 1000 0>; /* Max. bandwidth */ qcom,bus-vector-names = "MIN", "MAX"; qcom,instance-type = "sdcc"; }; ufs1: ufshc@1da4000 { compatible = "qcom,ufshc"; reg = <0x1da4000 0x3000>; Loading