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Commit 40f293ff authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'drm-intel-next' of git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel 

* 'drm-intel-next' of git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel:
  drm/i915: Add new GET_PIPE_FROM_CRTC_ID ioctl.
  drm/i915: Set HDMI hot plug interrupt enable for only the output in question.
  drm/i915: Include 965GME pci ID in IS_I965GM(dev) to match UMS.
  drm/i915: Use the GM45 VGA hotplug workaround on G45 as well.
  drm/i915: ignore LVDS on intel graphics systems that lie about having it
  drm/i915: sanity check IER at wait_request time
  drm/i915: workaround IGD i2c bus issue in kernel side (v2)
  drm/i915: Don't allow binding objects into the last page of the aperture.
  drm/i915: save/restore fence registers across suspend/resume
  drm/i915: x86 always has writeq. Add I915_READ64 for symmetry.
parents 8c21f341 08d7b3d1

drivers/gpu/drm/i915/i915_dma.c

+11 −2
Original line number Diff line number Diff line
@@ -1011,8 +1011,16 @@ static int i915_load_modeset_init(struct drm_device *dev) 
	/* Basic memrange allocator for stolen space (aka vram) */

	drm_mm_init(&dev_priv->vram, 0, prealloc_size);



	/* Let GEM Manage from end of prealloc space to end of aperture */

	i915_gem_do_init(dev, prealloc_size, agp_size);

	/* Let GEM Manage from end of prealloc space to end of aperture.

	 *

	 * However, leave one page at the end still bound to the scratch page.

	 * There are a number of places where the hardware apparently

	 * prefetches past the end of the object, and we've seen multiple

	 * hangs with the GPU head pointer stuck in a batchbuffer bound

	 * at the last page of the aperture.  One page should be enough to

	 * keep any prefetching inside of the aperture.

	 */

	i915_gem_do_init(dev, prealloc_size, agp_size - 4096);



	ret = i915_gem_init_ringbuffer(dev);

	if (ret)
@@ -1350,6 +1358,7 @@ struct drm_ioctl_desc i915_ioctls[] = { 
	DRM_IOCTL_DEF(DRM_I915_GEM_SET_TILING, i915_gem_set_tiling, 0),

	DRM_IOCTL_DEF(DRM_I915_GEM_GET_TILING, i915_gem_get_tiling, 0),

	DRM_IOCTL_DEF(DRM_I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, 0),

	DRM_IOCTL_DEF(DRM_I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, 0),

};



int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);

drivers/gpu/drm/i915/i915_drv.h

+4 −7
Original line number Diff line number Diff line
@@ -283,6 +283,7 @@ typedef struct drm_i915_private { 
	u8 saveAR[21];

	u8 saveDACMASK;

	u8 saveCR[37];

	uint64_t saveFENCE[16];



	struct {

		struct drm_mm gtt_space;
@@ -705,13 +706,8 @@ extern void intel_modeset_cleanup(struct drm_device *dev); 
#define I915_WRITE16(reg, val)	writel(val, dev_priv->regs + (reg))

#define I915_READ8(reg)		readb(dev_priv->regs + (reg))

#define I915_WRITE8(reg, val)	writeb(val, dev_priv->regs + (reg))

#ifdef writeq

#define I915_WRITE64(reg, val)	writeq(val, dev_priv->regs + (reg))

#else

#define I915_WRITE64(reg, val)	(writel(val, dev_priv->regs + (reg)), \

				 writel(upper_32_bits(val), dev_priv->regs + \

					(reg) + 4))

#endif

#define I915_READ64(reg)	readq(dev_priv->regs + (reg))

#define POSTING_READ(reg)	(void)I915_READ(reg)



#define I915_VERBOSE 0
@@ -790,7 +786,8 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller); 
		       (dev)->pci_device == 0x2E22 || \

		       (dev)->pci_device == 0x2E32)



#define IS_I965GM(dev) ((dev)->pci_device == 0x2A02)

#define IS_I965GM(dev) ((dev)->pci_device == 0x2A02 || \

			(dev)->pci_device == 0x2A12)



#define IS_GM45(dev) ((dev)->pci_device == 0x2A42)

drivers/gpu/drm/i915/i915_gem.c

+9 −0
Original line number Diff line number Diff line
@@ -1691,11 +1691,20 @@ static int 
i915_wait_request(struct drm_device *dev, uint32_t seqno)

{

	drm_i915_private_t *dev_priv = dev->dev_private;

	u32 ier;

	int ret = 0;



	BUG_ON(seqno == 0);



	if (!i915_seqno_passed(i915_get_gem_seqno(dev), seqno)) {

		ier = I915_READ(IER);

		if (!ier) {

			DRM_ERROR("something (likely vbetool) disabled "

				  "interrupts, re-enabling\n");

			i915_driver_irq_preinstall(dev);

			i915_driver_irq_postinstall(dev);

		}



		dev_priv->mm.waiting_gem_seqno = seqno;

		i915_user_irq_get(dev);

		ret = wait_event_interruptible(dev_priv->irq_queue,

drivers/gpu/drm/i915/i915_reg.h

+1 −0
Original line number Diff line number Diff line
@@ -526,6 +526,7 @@ 
#define   DPLLA_INPUT_BUFFER_ENABLE	(1 << 0)

#define D_STATE		0x6104

#define CG_2D_DIS	0x6200

#define DPCUNIT_CLOCK_GATE_DISABLE	(1 << 24)

#define CG_3D_DIS	0x6204



/*

drivers/gpu/drm/i915/i915_suspend.c

+24 −0
Original line number Diff line number Diff line
@@ -349,6 +349,18 @@ int i915_save_state(struct drm_device *dev) 
	for (i = 0; i < 3; i++)

		dev_priv->saveSWF2[i] = I915_READ(SWF30 + (i << 2));



	/* Fences */

	if (IS_I965G(dev)) {

		for (i = 0; i < 16; i++)

			dev_priv->saveFENCE[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));

	} else {

		for (i = 0; i < 8; i++)

			dev_priv->saveFENCE[i] = I915_READ(FENCE_REG_830_0 + (i * 4));



		if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))

			for (i = 0; i < 8; i++)

				dev_priv->saveFENCE[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));

	}

	i915_save_vga(dev);



	return 0;
@@ -371,6 +383,18 @@ int i915_restore_state(struct drm_device *dev) 
	/* Display arbitration */

	I915_WRITE(DSPARB, dev_priv->saveDSPARB);



	/* Fences */

	if (IS_I965G(dev)) {

		for (i = 0; i < 16; i++)

			I915_WRITE64(FENCE_REG_965_0 + (i * 8), dev_priv->saveFENCE[i]);

	} else {

		for (i = 0; i < 8; i++)

			I915_WRITE(FENCE_REG_830_0 + (i * 4), dev_priv->saveFENCE[i]);

		if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))

			for (i = 0; i < 8; i++)

				I915_WRITE(FENCE_REG_945_8 + (i * 4), dev_priv->saveFENCE[i+8]);

	}



	/* Pipe & plane A info */

	/* Prime the clock */

	if (dev_priv->saveDPLL_A & DPLL_VCO_ENABLE) {